Fundamental frequency response bounds of direct-form recursive switched-capacitor filters with capacitance mismatch

Circuits Syst Signal Process

2010

This paper presents a new CMOS analog fully differential voltage buffer, with large dynamic range and low harmonic distortion. Its design is based on the use of cross-coupled input differential pairs and internal current feedback. Two design approaches are proposed, with the objective of minimizing power consumption: one for switched-capacitor circuits and the other for Gm-C circuits. Design equations and simulation results are presented as well. Illustrative design examples are developed for a 0.35-µm CMOS technology using a power supply voltage of 2.5 V.

“…This discrepancy was minimized by Fig. 9 Cascode current mirror employing a cascode current mirror, as shown in Fig. 9.…”

Section: Gm-c Applicationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Fully Differential CMOS Voltage Buffer for Continuous- and Discrete-Time Applications

Barúqui

Circuits Syst Signal Process

2010

“…Denoting the standard deviation in unitary capacitance ratio errors as , whose value depends on fabrication process parameters and on capacitor size and geometry, then the lower and upper boundary curves enclosing the feasible magnitude frequency responses of direct-form SC filters, are given, respectively, by [6] (2) and (3) where the frequency-dependent factor of the frequency response deviation can be written as (4) where , and and denote passband and stopband frequencies, respectively.…”

Section: B Optimum Approach For Sc Implementionmentioning

confidence: 99%

“…The design of SC IIR filters has been usually based on some -to-transformation of a classical analog approximation, leading to transfer functions with equal numerator and denominator orders. It has recently been shown, however, that by formulating the approximation problem in the -domain to produce transfer functions with denominator order smaller than the numerator order, low sensitivity can theoretically be achieved with a direct-form topology [6]. Our paper will focus on the practical realization of SC IIR filters that retain the simplicity and advantages of direct-form realizations, yet achieving very low sensitivity to capacitance ratios.…”

Section: Introductionmentioning

confidence: 98%

Optimum design and implementation of IIR SC filters using small-order FIR cells

Pereira

IEEE Trans. Circuits Syst. II

2002

Self Cite

A novel approach for designing infinite impulse response (IIR) switched-capacitor filters, based on the optimum allocation of poles and zeros of a transfer function, implemented by a direct-form topology using finite-impulse response (FIR) cells as basic building blocks is presented. As a consequence, low sensitivity with respect to capacitance ratio errors in both passband and stopband frequencies, low power consumption, and improved group delay response are achieved. Comparisons with classical IIR and linear-phase FIR filter designs are made. An illustrative design example including simulation and experimental results obtained with a prototype filter are provided.Index Terms-Delay equalizers, direct form, pole and zero assignments, sensitivity, switched-capacitor filters.

“…Differential buffers have been employed as basic building blocks in time delay lines in switched capacitor (SC) realizations of discrete-time transfer functions [1], [2], and in continuous-time filters, as for example, the ones derived by the gm-C technique [3]. Buffer amplifiers also play important role in interfacing on-chip differential circuits with the external world.…”

Section: Introductionmentioning

confidence: 99%

A new approach for the design of CMOS voltage buffers for switched-capacitor and gm-C filters

Barúqui

2009 IEEE International Symposium on Circuits and Systems

2009

Buffers are widely employed as basic building blocks in time delay lines and in interfacing integrated circuits with the external world. This paper presents a new CMOS analog fully differential voltage buffer developed for minimum power consumption, large dynamic range and low harmonic distortion. Its design is based on the use of cross-coupled input differential pairs and internal current feedback. Two design approaches are proposed: one for switched-capacitor circuits and the other for gm-C circuits. Illustrative design examples are developed for a 0.35 -"m"m CMOS technology using a power supply voltage of 2.5 V. Spice simulations using BSIM3 device models are shown to support the theory.