Fundamentals and Failures in Die Preparation for 3D Packaging

Shi, Hua‐Tian; Erasenthiran, Poonjolai

doi:10.1007/978-3-319-44586-1_5

Cited by 4 publications

(2 citation statements)

References 51 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The most recent developments in digital electronics, including the IoT, artificial intelligence (AI), 5G networks, and HPC, have called for computers with exceptional speed and computing abilities [8,9]. Moore's law predicts that transistor density per unit area in microchips would increase exponentially to meet these criteria, even as chip size decreases [10]. The technology for mass-producing 5 nm chips has already been developed by popular semiconductor manufacturers like Samsung and Taiwan Semiconductor and Manufacturing Company (TSMC) and is on track for future commercialization.…”

Section: Introductionmentioning

confidence: 99%

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Jang,

Sharma,

Jung

2023

Materials

View full text Add to dashboard Cite

Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency.

show abstract

Section: Introductionmentioning

confidence: 99%

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Jang,

Sharma,

Jung

2023

Materials

View full text Add to dashboard Cite

show abstract

“…The recent advancements in digital electronics such as the Internet of Things (IoT), Artificial Intelligence (AI), fifth-generation (5G) communication, and high-performance computer (HPC) demand computers with unbelievable memory, speed, and computation power [1,2]. To meet the demands of growing technology, the number of transistors per unit area in the microchip increases exponentially as per Moore's law, which is accompanied by the downscaling of the chip size [3]. Currently, major semiconducting companies such as Samsung and TMSC have developed the 5 nm node process for mass production and are looking forward to developing 3 nm nodes in the near future.…”

Section: Introductionmentioning

confidence: 99%

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Cho

Seo

Kim

et al. 2021

Metals

View full text Add to dashboard Cite

With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

show abstract