Further investigation of EUV process sensitivities for wafer track processing

Abstract

As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work 1 , processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACT™12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.

A summary of the current development of developing technology in the field of integrated circuit manufacturing

“…The common development defects are peeling, bridging, adhesion, etc. [6]. The defective developing nozzle or the process is the root reason, which lead to unevenly developing and developing defects.…”

Application specific ratings for lithography process filters

“…Microbridge precursors are the targeted defect source, because of their relevance and potential impact on DUV [2][3][4][5][6] and EUV litho processes [8,9] . As shown in Figure 3, microbridge reduction by filtration is more sensitive to membrane material than to membrane removal [5] .…”

A Comprehensive Review of EUV Resist Materials and Processing at Selete

“…To provide possible solutions, there is a trend in individual and collaborative efforts between research consortiums, universities, and resist material developers on the investigation of new EUV resist platform and material designs [3][4][5][6][7][8][9] . This is also true for the conceptualization and application of alternative resist processes which have shown significant potential as pattern sizes become smaller [10][11][12][13] . In the last five years, Selete has been actively advancing EUV lithography (EUVL) as the next lithographic technology for semiconductor manufacturing.…”