Further Studies on Space Compression in Embedded Cores-Based Systems Using Fault Graded Output Merger

Abstract

The design of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the synthesis of cores-based system-on-chips (SOCs). This paper reports on further studies on a space compression technique recently developed by the authors that facilitates designing such circuits using pseudorandom and compact test sets, with the basic objective of reducing the storage requirements for the circuit under test (CUT) while still retaining the fault coverage information. The compression technique uses the concept offault graded output merger based on identifying strong and weak compatibility relations in response data. The proposed method guarantees design with full fault coverage for single stuck-line faults together with low CPU simulation time and acceptable area overhead Simulation runs on ISCAS 89full-scan sequential benchmark circuits with ATALANTA and FSIM programs as reported herein confirm once again the usefulness of the suggested approach.