FuSE - a hardware accelerated HDL fault injection tool

Abstract

The ongoing miniaturization of digital circuits makes them more and more susceptible to faults which also complicates the design of fault tolerant systems. In this context fault injection plays an important role in the process of fault tolerance validation. As a result many fault injection tools have emerged during the last decade. However these tools only operate on specific domains and can therefore be referred to as hardware-or software-, simulation-or emulation based techniques.In this paper we present FuSE, a single fault injection tool which covers multiple domains as well as different fault injection purposes. FuSE has been designed for usage with the SEmulator R -an FPGA-based hardware accelerator. The created tool set has been fully automated for the fault injection process and only requires a VHDL description and a testbench of the circuit under test. FuSE can then perform fault injection experiments with a diagnostic resolution that is known from simulation-based approaches, but at a speed that even handles long running experiments with ease.

RASP-FIT: A Fast and Automatic Fault Injection Tool for Code-Modification of FPGA Designs

“…Authors studied the recently developed fault injection tools based on instrumentation technique in the FPGA development flow, such as, tools that work on the net-list developed after the synthesis process [14], [15], [16], some tools based on the instrumentation technique on the code level [18], [17], and using some hybrid techniques (simulation/emulation) [19], [20], [21], [22]. HDL environment is able to generate a list of faults and it is used for fault emulation/simulation of the target system.…”

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

“…• FuSE [90] proposes the fault simulation using SEmulator, where both simulation based FI and FPGA accelerated FI can be switched. The integration is transparent so that both fault propagation and huge number of FI experiments are realized simultaneously.…”

Flattening: An efficient approach to improving the performance of conventional MINs

“…In previous studies [30][31][32] simulators based on hardware definition language have been applied. Digital design tools such as Synopsys DC, Quartus, and Leonardo report parameters such as power consumption and area.…”