Future Graphics Architectures

Mark, William R.

doi:10.1145/1365490.1365501

Cited by 9 publications

(5 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…GPUs have been introduced for computationally intensive processes in the graphics pipeline, and primarily for interactive 3-D graphics such as games. Many computationally intensive operations in the graphics pipeline are now processed by GPUs [34].…”

Section: Computer Graphicsmentioning

confidence: 99%

Algorithm/Architecture Co-Exploration of Visual Computing on Emergent Platforms: Overview and Future Prospects

Lee

Chen

Mattavelli

et al. 2009

IEEE Trans. Circuits Syst. Video Technol.

View full text Add to dashboard Cite

Abstract-Concurrently exploring both algorithmic and architectural optimizations is a new design paradigm. This survey paper addresses the latest research and future perspectives on the simultaneous development of video coding, processing, and computing algorithms with emerging platforms that have multiple cores and reconfigurable architecture. As the algorithms in forthcoming visual systems become increasingly complex, many applications must have different profiles with different levels of performance. Hence, with expectations that the visual experience in the future will become continuously better, it is critical that advanced platforms provide higher performance, better flexibility, and lower power consumption. To achieve these goals, algorithm and architecture co-design is significant for characterizing the algorithmic complexity used to optimize targeted architecture. This paper shows that seamless weaving of the development of previously autonomous visual computing algorithms and multicore or reconfigurable architectures will unavoidably become the leading trend in the future of video technology.

show abstract

Section: Computer Graphicsmentioning

confidence: 99%

Algorithm/Architecture Co-Exploration of Visual Computing on Emergent Platforms: Overview and Future Prospects

Lee

Chen

Mattavelli

et al. 2009

IEEE Trans. Circuits Syst. Video Technol.

View full text Add to dashboard Cite

show abstract

“…By offering unprecedented processing power (e.g., 4300GFLOPS by AMD's Radeon HD7900 GPU [2]) on a single chip, GPUs are dramatically changing the landscape of modern computing. Future GPUs will continue to offer ever-growing computing throughput and increasing flexibility by supporting more parallel processing patterns [3].…”

Section: Introductionmentioning

confidence: 99%

Exploiting the Task-Pipelined Parallelism of Stream Programs on Many-Core GPUs

Chen

et al. 2013

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYBy exploiting data-level parallelism, Graphics Processing Units (GPUs) have become a high-throughput, general purpose computing platform. Many real-world applications especially those following a stream processing pattern, however, feature interleaved task-pipelined and data parallelism. Current GPUs are ill equipped for such applications due to the insufficient usage of computing resources and/or the excessive offchip memory traffic. In this paper, we focus on microarchitectural enhancements to enable task-pipelined execution of data-parallel kernels on GPUs. We propose an efficient adaptive dynamic scheduling mechanism and a moderately modified L2 design. With minor hardware overhead, our techniques orchestrate both task-pipeline and data parallelisms in a unified manner. Simulation results derived by a cycle-accurate simulator on real-world applications prove that the proposed GPU microarchitecture improves the computing throughput by 18% and reduces the overall accesses to off-chip GPU memory by 13%.

show abstract

“…CPUs, on the other hand, are more optimized for sequential code containing many datadependent branch instructions. The model of computation of GPUs is therefore unlike the traditional one of CPUs, even though they are converging [17].…”

Section: Introductionmentioning

confidence: 99%

On the Correctness of the SIMT Execution Model of GPUs

Habermaier

Knapp

2012

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. GPUs are becoming a primary resource of computing power. They use a single instruction, multiple threads (SIMT) execution model that executes batches of threads in lockstep. If the control flow of threads within the same batch diverges, the different execution paths are scheduled sequentially; once the control flows reconverge, all threads are executed in lockstep again. Several thread batching mechanisms have been proposed, albeit without establishing their semantic validity or their scheduling properties. To increase the level of confidence in the correctness of GPU-accelerated programs, we formalize the SIMT execution model for a stack-based reconvergence mechanism in an operational semantics and prove its correctness by constructing a simulation between the SIMT semantics and a standard interleaved multi-thread semantics. We also demonstrate that the SIMT execution model produces unfair schedules in some cases. We discuss the problem of unfairness for different batching mechanisms like dynamic warp formation and a stack-less reconvergence strategy.

show abstract

Future Graphics Architectures

Cited by 9 publications

References 8 publications

Algorithm/Architecture Co-Exploration of Visual Computing on Emergent Platforms: Overview and Future Prospects

Algorithm/Architecture Co-Exploration of Visual Computing on Emergent Platforms: Overview and Future Prospects

Exploiting the Task-Pipelined Parallelism of Stream Programs on Many-Core GPUs

On the Correctness of the SIMT Execution Model of GPUs

Contact Info

Product

Resources

About