Future on-chip interconnect metallization and electromigration

Hu, C.‐K.; Kelly, James; Huang, Huai; Motoyama, K.; Shobha, H.; Ostrovski, Y.; Chen, J. H-C; Patlolla, R.; Peethala, B.; Adusumilli, Praneet; Spooner, T.; Quon, R.; Gignac, L.; Breslin, Chris; Lian, Guoda; Ali, Muhammad Zeshan; Benedict, J.; Lin, Xuan; Smith, Sharon L.; Kamineni, V.; Zhang, X.; Mont, Frank W.; Siddiqui, S.; Baumann, F.H.

doi:10.1109/irps.2018.8353597

Cited by 60 publications

(40 citation statements)

References 18 publications

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“…38,39 In addition, Ru is also promising as back end and middle-of-line interconnect metal due to its potential to be used with much thinner barriers 22 and its resistance to electromigration. 40,41 Recent investigations on Ru films and wires are promising, indicating a low resistivity scaling 19,23,25,42 and better conduction than Cu for line widths < 16 nm. 40 Studies on polycrystalline Ru films suggest a high specularity for electron surface scattering with a bulk mean free path λ = 6.6 nm that matches the calculated prediction of 6.4-6.6 nm.…”

Section: Introductionmentioning

confidence: 99%

Resistivity size effect in epitaxial Ru(0001) layers

Milosevic

Kerdsongpanya

Zangiabadi

et al. 2018

Journal of Applied Physics

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Epitaxial Ru(0001) layers are sputter deposited onto Al2O3(0001) substrates and their resistivity ρ measured both in situ and ex situ as a function of thickness d = 5-80 nm in order to quantify the resistivity scaling associated with electron-surface scattering. All layers have smooth surfaces with a root-mean-square roughness < 0.4 nm and exhibit an epitaxial relationship with the substrate: Ru[0001]║Al2O3[0001] and Ru[ 0 1 10 ]║Al2O3[ 0 2 11 ], suggesting negligible resistivity contributions from geometric surface roughness and grain boundary scattering. The room temperature ρ vs d data is well described by the semiclassical Fuchs and Sondheimer (FS) model, indicating a bulk electron mean free path λ = 6.7 ± 0.3 nm. Electron scattering at the Ru(0001) surface is distinctly different from the known Cu(001) surface: Its scattering specularity is unaffected by oxygen exposure but dependent on temperature and/or the environment, as indicated by a 43% decrease in the measured ρo×λ product with decreasing temperature from 295 to 77 K. Transport simulations employing the ruthenium electronic structure determined from firstprinciples and a constant relaxation time approximation indicate that the resistivity is strongly (by a factor of two) affected by both the transport direction and the terminating surfaces. This is quantified with a room temperature effective mean free path λ * which is relatively small for transport along the hexagonal axis independent of layer orientation (λ * = 4.3 nm) and for (0001) terminating surfaces independent of transport direction (λ * = 4.5 nm), but increases, for example, to λ * = 8.8 nm for (1120) surfaces and transport along [1100]. Direct experiment-simulation comparisons show a 12% and 49% higher λ from experiment at 77 and 295 K, respectively, indicating limitations of the semi-classical transport simulations despite the correct accounting of Fermi surface and Fermi velocity anisotropies. The overall results demonstrate a low resistivity scaling for Ru, suggesting that 10 nm half-pitch Ru interconnect lines are approximately 2 times more conductive than comparable Cu lines.

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Section: Introductionmentioning

confidence: 99%

Resistivity size effect in epitaxial Ru(0001) layers

Milosevic

Kerdsongpanya

Zangiabadi

et al. 2018

Journal of Applied Physics

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“…As explained in detail above, the dimensions scaling of the Cu-based process has degraded electromigration. As a replacement, three main alternatives can now be considered: Co and Ru, as well as Cu with Co cap showed highly reliable electromigration, with activation energies of 2.4~3.1 eV, 1.9 eV, and 1.5~1.7 eV, respectively [83]. These data provide a very promising solution for the BEOL of 10 nm and below platforms.…”

Section: Beol: Next Generation For Materials Processes and Related Drsmentioning

confidence: 91%

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 µm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations.Keywords: back end of line; layout design rules; copper technology; inter-metal dielectric time-dependent dielectric breakdown (IMD-TDDB) M2-M5) have similar or slightly increased thicknesses when compared with the M1 layer, and are mostly used for connections between various devices. Semi-global (M6-M7, 0.35-0.9 µm) and global (M8, 0.9-3.3 µm) lines are used for power buses, transmission lines, and inductors.In order to achieve a tight pitch of M1 and semi-global lines with a high-density design, interconnects are used to connect high-density-logic transistors, standard cells, and other functional blocks in a system on chip (SoC). In general, application-specific integrated circuits (ASICs) and SoCs tend to use a combination of interconnect metals with a large number of MI lines (semi-global) for applications such as highly parallel graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and multi-core smartphone processors (multiple central processing unit (CPU) and GPU cores). In contrast, devices for applications of radio frequency CMOS (RFCMOS), millimeter wave (mmWave), and WiFi use several layers of semi-global and global lines for inductors, transmission lines, and more. From a practical point of view, the set of rules relating to specific types of interconnect do not change based on their use in various applications. This is because many electronic design automation (EDA) tools such as design rule checks (DRCs), BEOL RC modeling, and even dummy fill insertions also need to be adjusted. Instead, the platform process design kit (PDK) includes a large set of metal combinations so that the designer may select one based on their integrated circuit (IC) needs. For example, WiFi ICs, designed using the 65 nm RFCMOS...

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“…To include the out-of-plane interactions, DFT-D2 corrections [35] have been incorporated. Top three SE based barrierless via metals (Co, Ru, W) [6], [36] form the prospective choice for the via metal as they minimize the resistance at sub-10 nm nodes. Contact resistance of any interface essentially translates to determining the available states with matching energy and k-vectors on both sides of the interface, Table showing the experimentally obtained EM activation energies of the via metals [6], [36].…”

Section: Identification Of Optimal Via Metalmentioning

confidence: 99%

“…(a) Resistance per unit length versus wire width for Cu, Co, and Ru wires by single damascene process, and Co and DMLG wires by SE, with AR of 1 and 2. The Cu, Co, and Ru wire resistance by damascene process is estimated from an empirical model [6], Co wire resistance by SE is estimated from the model in [7], and DMLG wire resistance is calculated from an analytical model based on the Landauer approach [8] with consideration of DMLG bandgap opening (for sub-20 nm wire widths) and a doping level of |E F | = 0.6 eV. All the models are calibrated with measured data.…”

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confidence: 99%

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Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias

Agashiwala

Jiang

Parto

et al. 2021

IEEE Trans. Electron Devices

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Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, selfheating (SH), electromigration (EM), and various integration challenges. Even though single-level scaled graphene wires have been shown to possess better performance and reliability with respect to dual-damascene (DD) and SE-enabled metal wires, a multi-level graphene interconnect technology (with vias) has remained elusive, which is of paramount importance for its integration in future technology nodes. This work, for the first time, addresses that need by engineering a CMOS-compatible solid-phase growth technique to yield large-area multilayer graphene (MLG) on dielectric (SiO 2) and metal (Cu) substrates and subsequently demonstrating multi-level MLG interconnects with metal vias. Using rigorous theoretical and experimental analyses, we demonstrate that multi-level MLG interconnects with metal vias undergo < 2% change in the via resistance under accelerated stress conditions, demonstrating its superior reliability against SH and EM, making them ideal candidates for sub-10 nm nodes.

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Future on-chip interconnect metallization and electromigration

Cited by 60 publications

References 18 publications

Resistivity size effect in epitaxial Ru(0001) layers

Resistivity size effect in epitaxial Ru(0001) layers

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias

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