FUZYE: A Fuzzy ${c}$ -Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms

Canelas, António; Póvoa, Ricardo; Martins, Ricardo; Lourenço, Nuno; Guilherme, Jorge; Carvalho, João Paulo; Horta, Nuno

doi:10.1109/tcad.2018.2883978

Cited by 20 publications

(12 citation statements)

References 42 publications

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“…In [21], a similar methodology is proposed, where the candidate solutions are subject to a small number of MC simulations to perform variability analysis, which allows allocating a different number of MC simulations to different candidate solutions from a total budget. In [22], clustering is used to select a subset of the representative solutions to be subject to MC analysis at each iteration. Some other works adopted low-discrepancy sequences methods to reduce the necessary number of MC samples; however, their use in optimization-based methodologies still demands many simulations [23], [24].…”

Section: A Rf Ic Variability-aware Synthesismentioning

confidence: 99%

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

et al. 2021

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This paper presents an innovative yield-aware synthesis strategy based on a hierarchical bottom-up methodology that uses a multiobjective evolutionary optimization algorithm to design a complete radiofrequency integrated circuit from the passive component level up to the system level. Within it, performances' calculation aims for the highest possible accuracy. A surrogate model calculates the performances for the inductive devices, with accuracy comparable to full electromagnetic simulation; and, an electrical simulator calculates circuit-and system-level performances. Yield is calculated using Monte-Carlo (MC) analysis with the foundry-provided models without any model approximation. The computation of the circuit yield throughout the hierarchy is estimated employing parallelism and reducing the number of simulations by performing MC analysis only to a reduced number of candidate solutions, alleviating the computational requirements during the optimization. The yield of the elements not accurately evaluated is assigned using their degree of similitude to the simulated solutions. The result is a novel synthesis methodology that reduces the total optimization time compared to a complete MC yield-aware optimization. Ultimately, the methodology proposed in this work is compared against other methodologies that do not consider yield throughout the system's complete hierarchy, demonstrating that it is necessary to consider it over the entire hierarchy to achieve robust optimal designs.

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Section: A Rf Ic Variability-aware Synthesismentioning

confidence: 99%

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

et al. 2021

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“…9a shows a gate connected couple ( 14) gcc 1 in two current biases cb 1 , cb 2 . The gate connected couple (15). The transistors N 3 , N 4 are therefore part of gcc 1 , vdp 1 and cb 1 or cb 2 .…”

Section: F Multiple Assignments Of Transistors To Functional Blocksmentioning

confidence: 99%

“…Copyright may be transferred without notice, after which this version may no longer be accessible. which have to be set up for each new op-amp, and simulationbased numerical optimization approaches [9]- [15], which need a CAD tool setup and value seeding for each netlist. It is also positioned between optimization-based structural synthesis approaches [16]- [20] that create a large number of variants some of them being impractical or redundant, and approaches without involvement of optimization that investigate only a very small number of variants [21], [22].…”

Section: Introductionmentioning

confidence: 99%

A Functional Block Decomposition Method for Automatic Op-Amp Design

Abel¹,

Neuner²,

Graeb³

2020

Preprint

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This paper presents a method to decompose an opamp into its functional blocks. The method is able to recognize functional blocks on a high level of abstraction as loads or fification stages which have a large set of possible structural implementations. The paper presents a hierarchical library of functional blocks. With every hierarchy level the structural representation of the functional blocks becomes more variable while its function emerges. We use the hierarchical order to automatically compute the functional decomposition of an opamp given as a flat netlist. Experimental results will illustrate the method. The functional block decomposition enables a comprehensive formalization of design knowledge for computeraided design of op-amps. This is the first paper of a selection of three paper on automatic op-amp design. In [1], the design equations that correspond to the functional blocks are presented. Based on the op-amp decomposition and the design equation, op-amps are automatically sized. In [2], an automatic op-amp structure synthesis method will be presented, which is based on the functional block decomposition presented in the following and the design equations from [1].

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“…Recently, some analogue circuit yield optimisation approaches have been proposed [13][14][15][16]. Most of these approaches are based on evolutionary algorithms [13][14][15], but ref.…”

Section: Introductionmentioning

confidence: 99%

A four‐stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms

Yaseri

Maghami

Radmehr

2022

IET Computers & Digital Tech

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A high yield estimation is necessary for designing analogue integrated circuits. In the Monte‐Carlo (MC) method, many transistor‐level simulations should be performed to obtain the desired result. Therefore, some methods are needed to be combined with MC simulations to reach high yield with high speed at the same time. In this paper, a four‐stage yield optimisation approach is presented, which employs computational intelligence to accelerate yield estimation without losing accuracy. Firstly, the designs that met the desired characteristics are provided using critical analysis (CA). The aim of utilising CA is to avoid unnecessary MC simulations repeating for non‐critical solutions. Then in the second and third stages, the shuffled frog‐leaping algorithm and the Non‐dominated Sorting Genetic Algorithm‐III are proposed to improve the performance. Finally, MC simulations are performed to present the final result. The yield value obtained from the simulation results for two‐stage class‐AB Operational Transconductance Amplifer (OTA) in 180 nm Complementary Metal‐Oxide‐Semiconductor (CMOS) technology is 99.85%. The proposed method has less computational effort and high accuracy than the MC‐based approaches. Another advantage of using CA is that the initial population of multi‐objective optimisation algorithms will no longer be random. Simulation results prove the efficiency of the proposed technique.

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FUZYE: A Fuzzy ${c}$ -Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms

Cited by 20 publications

References 42 publications

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

A Functional Block Decomposition Method for Automatic Op-Amp Design

A four‐stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms

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