G-link and gigabit Ethernet compliant serializer for LHC data transmission

Moreira, P; Toifl, Thomas; Kluge, A.; Cervelli, G.; Faccio, F.; Marchioro, A.; Christiansen, J.

doi:10.1109/nssmic.2000.949860

Cited by 67 publications

(54 citation statements)

References 5 publications

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“…Two high-integration MTP 12-fiber optical receiver modules and a dual LC receiver module are to be used. The output serialization and laser driving tasks are currently carried out by the CERN's GOL (gigabit optical link) IC [5], which plugs to the main ROS board in a mezzanine board that also includes the VCSEL.…”

Section: Upgrade To the Dt Readout Systemmentioning

confidence: 99%

Upgrade of the second level of the readout electronics for the CMS drift tubes subdetector

Tobar

2011

2011 IEEE Nuclear Science Symposium Conference Record

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The readout server (ROS), which constitutes the second level of the CMS drift tubes (DT) subdetector readout architecture, is a complex VME 9U board, currently placed in the CMS cavern, in the racks on one side of the detector wheels. The planned upgrade of DT electronics for 2013-2014 includes the relocation of all the second level of readout and trigger electronics in the CMS counting room, allowing among others, the future redesign of a higher performance ROS board based on commercial devices with no radiation tolerance requirements. Simulation studies have been carried out in order to assess the system's performance under the increased luminosity (10 35 cm −2 s −1 ) planned for the HL-LHC upgrade, ca. 2020. Results show that the ROS board could become a limiting factor due to the event processing time. The capabilities of currently-available FPGAs allow incorporating most of the ROS functions (input deserialization, input buffer, data processing and multiplexing, slow control interface, test-mode operation) into a single device. In particular, Virtex-6 and Spartan-6 series are being considered. In both families, fully-automatic asynchronous deserialization is carried out by the gigabit transceivers, which are not suitable for our application due to the minimum data rate and reduced availability. Nevertheless, asynchronous data reception can be carried out by making use of the dedicated deserializers present in each of the I/O tiles, plus some additional logic and clocking resources. The improved performance of these devices (as compared with current ROS technology) allows reducing the event processing time, effectively increasing maximum system's operation frequency.Presented at IEEE-nss-mic-rtsd2011: IEEE2011: Nuclear Science Symposium and Medical Imaging Conference Upgrade of the Second Level of the Readout Electronics for the CMS Drift Tubes SubdetectorÁlvaro Navarro-Tobar on behalf of the CMS DT group Abstract-The readout server (ROS), which constitutes the second level of the CMS drift tubes (DT) subdetector readout architecture, is a complex VME 9U board, currently placed in the CMS cavern, in the racks on one side of the detector wheels. The planned upgrade of DT electronics for 2013-2014 includes the relocation of all the second level of readout and trigger electronics in the CMS counting room, allowing among others, the future redesign of a higher performance ROS board based on commercial devices with no radiation tolerance requirements.Simulation studies have been carried out in order to assess the system's performance under the increased luminosity (10 35 cm −2 s −1 ) planned for the HL-LHC upgrade, ca. 2020. Results show that the ROS board could become a limiting factor due to the event processing time.The capabilities of currently-available FPGAs allow incorporating most of the ROS functions (input deserialization, input buffer, data processing and multiplexing, slow control interface, test-mode operation) into a single device. In particular, Virtex-6 and Spartan-6 series are being consi...

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Section: Upgrade To the Dt Readout Systemmentioning

confidence: 99%

Upgrade of the second level of the readout electronics for the CMS drift tubes subdetector

Tobar

2011

2011 IEEE Nuclear Science Symposium Conference Record

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“…For the cosmic-ray data-taking, the Pixel Detector links also operated at 40 MBits/s. The TRT uses shielded twistedpair lines to transfer data to a patch panel inside the muon spectrometer, where up to 31 lines are multiplexed [15] into one 1.6 Gbits/s optical link.…”

Section: The Atlas Inner Detectormentioning

confidence: 99%

The ATLAS Inner Detector commissioning and calibration

Aad¹,

Abbott²,

Abdallah³

et al. 2010

Eur. Phys. J. C

101

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The ATLAS Inner Detector is a composite tracking system consisting of silicon pixels, silicon strips and straw tubes in a 2 T magnetic field. Its installation was completed in August 2008 and the detector took part in data-taking with single LHC beams and cosmic rays. The initial detector operation, hardware commissioning and insitu calibrations are described. Tracking performance has been measured with 7.6 million cosmic-ray events, collected using a tracking trigger and reconstructed with modular pattern-recognition and fitting software. The intrinsic hit efficiency and tracking trigger efficiencies are close to 100%. Lorentz angle measurements for both electrons and holes, specific energy-loss calibration and transition radiation turn-on measurements have been performed. Different alignment techniques have been used to reconstruct the detector geometry. After the initial alignment, a transverse impact parameter resolution of 22.1 ± 0.9 µm and a relative momentum resolution σ p /p = (4.83 ± 0.16) ×

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“…The PILOT2003 chip [7,8] initiates the read-out of the pixel chips and controls the ANAPIL chip, which provides analog bias voltages to the pixel chips and measures supply, bias voltages and the temperature on the detector. Once read-out has been initiated the nonzero-suppressed data are sent from the pixel chips via the PILOT2003 [18] and an 800 Mbit/s G-link compatible optical link driver chip GOL [9,10] and an optical fiber to the control room. The description of row data format is in [16].…”

Section: B General Readout Schemementioning

confidence: 99%

The ALICE silicon pixel detector readout electronics

Krivda

Bán

Burns

et al. 2010

Nuclear Instruments and Methods in Physics Research Section A:

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The ALICE silicon pixel detector (SPD) constitutes the two innermost layers of the ALICE inner tracker system [1]. The SPD contains 10 million pixels segmented in 120 detector modules (half staves), which are connected to the offdetector electronics with bidirectional optical links. Raw data from the on-detector electronics are sent to 20 FPGA-based processor cards (Routers) each carrying three 2-channel linkreceiver daughter-cards. The routers process the data and send them to the ALICE DAQ system via the ALICE detector data link (DDL). The SPD control, configuration and data monitoring is performed via the VME interface of the routers. This paper describes the detector readout and control via the off-detector electronics.

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G-link and gigabit Ethernet compliant serializer for LHC data transmission

Cited by 67 publications

References 5 publications

Upgrade of the second level of the readout electronics for the CMS drift tubes subdetector

Upgrade of the second level of the readout electronics for the CMS drift tubes subdetector

The ATLAS Inner Detector commissioning and calibration

The ALICE silicon pixel detector readout electronics

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