G4-FET modeling for circuit simulation by adaptive neuro-fuzzy training systems

Aghababa, Hossein; Ebrahimi, Behzad; Saremi, Mehdi; Moalemi, V.; Forouzandeh, Behjat

doi:10.1587/elex.9.881

Cited by 15 publications

(5 citation statements)

References 11 publications

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“…The electrical behavior of the MOSFETs changes in nano scale regime. 22,23 So, new techniques should be used to overcome critical problems. Controlling short channel effects is one of the main goals in this paper.…”

Section: Resultsmentioning

confidence: 99%

“…One of them is the reduced maximum lattice temperature of the IPR-MOSFET. The ideal value for SS is about 60 (mV/decade) which happens at 300 K. for the other temperatures, the following equation is useful to obtain SS: [15][16][17][18][19][20][21][22][23][24] SS ≈ 60 mV T 300 K [1] The lower maximum lattice temperature of the proposed structure causes lower subthreshold slope.…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Reducing Floating Body and Short Channel Effects in Nano Scale Transistor: Inserted P⁺Region SOI-MOSFET

Mehrad

2016

ECS J. Solid State Sci. Technol.

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Short channel effects are the main challenges in nano scale devices. The novel way for controlling this problem is studied in this paper. Moreover, floating body effect is reduced significantly. The goal of this work is inserting P+ region in the active region and buried oxide. The P+ region is considered in the N+-source and the different doping of N+ and P+ which results in tunneling holes from valence band to conduction band. So, the accumulated holes in the channel reduces and floating body effect controls, effectively. In this case the potential between drain and left side of the channel decreases and DIBL reduces. Moreover, the simulation with ATLAS simulator shows that inserting P+ region in SOI-MOSFET (IPR-MOSFET) causes low lattice temperature and subthreshold swing in comparison to conventional SOI-MOSFET (C-MOSFET). So, the benefits of the proposed structure could be applicable in nano devices.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Reducing Floating Body and Short Channel Effects in Nano Scale Transistor: Inserted P⁺Region SOI-MOSFET

Mehrad

2016

ECS J. Solid State Sci. Technol.

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“…To overcome the aforementioned problem more than one gate are used to control the channel, called multiple gate field effect transistor (MUGFET) [1]. A MUGFET such as double gate MOSFET [2], FinFET [3][4][5] and gate all around structures [5,6] are used where the gate is wrapped around the thin silicon film, which provides better electrostatic control. These semiconductor devices are junction based and the formation of such a sharp junction for an ultra scaled device is quite challenging.…”

Section: Introductionmentioning

confidence: 99%

Analog performance investigation of misaligned double gate junctionless transistor

Amin

Sarin

2015

J Comput Electron

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In this paper, the analog performance of a misaligned double gate junctionless transistor (DGJLT) is demonstrated for the first time. The gate misalignment can occur on either source side (MA_S) or at drain side (MA_D). Since misalignment is a type of degradation that occurs during device fabrication, the idea behind this demonstration is to analyze the impact of gate misalignment on DGJLT. The analog performance parameters analyzed are, transconductance (g m ), output conductance (g ds ), early voltage (V EA ) and intrinsic gain (A VO ). They are compared with a double gate inversion mode transistor (DGIMT) under same gate misalignment condition. A DGJLT is found to have better tolerance to gate misalignment compared to DGIMT. MA_S configuration of a DGJLT shows better analog performance compared to MA_D configuration where as for DGIMT it shows better performance for MA_D compared to MA_S configuration.

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“…1 Their good electrical characteristics in nano scale have made them appropriate for integrating circuits in large scale. [2][3][4][5] Moreover, they are widely used in digital Complementary Metal Oxide Semiconductor (CMOS) logic. 6 Primary MOSFETs were developed on a silicon body (substrate) which makes some problems.…”

mentioning

confidence: 99%

Improved Device Performance in Nano Scale Transistor: An Extended Drain SOI MOSFET

Mehrad

Zareiee

2016

ECS J. Solid State Sci. Technol.

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Reducing the size of SOI MOSFET especially in nano regime for applying them in Integrated Circuits is difficult, because of the important problems of Short Channel Effects (SCE). These effects reduce the reliability of the device and it is objective to decrease them. In this paper, the goal is to propose a new structure for SOI MOSFET to improve SCEs. In this case the, the form of drain and channel is changed to obtain more reliable device. In this case, the drain region is extended into the channel improving the performance of the device. The drain has higher doping concentration, which causes better performance. The simulation with two dimensional ATLAS simulator shows that the new structure has better performance than the conventional one in cases of off current, subthreshold slope, threshold voltage, DIBL, maximum electron temperature and drain current which leads to more reliable device.Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have been introduced for amplifying or switching the electronic signals. 1 Their good electrical characteristics in nano scale have made them appropriate for integrating circuits in large scale. 2-5 Moreover, they are widely used in digital Complementary Metal Oxide Semiconductor (CMOS) logic. 6 Primary MOSFETs were developed on a silicon body (substrate) which makes some problems. The considerable capacitances between source/drain and substrate, high leakage current, latch up phenomena, and high consumption power, are the problems which are created because of the silicon substrate. 7,8 To overcome them, Silicon On Insulator (SOI) technology is introduced which can reduce these problems effectively. 9 This technology is composed of three layers: a silicon layer at the bottom, an Insulator layer (normally SiO 2 ) in the middle, and a silicon layer as an active region at the top of the structure. The insulator in the middle of the structure has an important role at which the capacitances between source-drain and the insulator are small. The leakage current gets small because of the small conductivity of the insulator. Besides, the consumption power is reduced and the latch up phenomena is approximately omitted. Therefore, SOI MOSFET technology is very useful for growing the electronic industry. 10 However, in nano scale regime, short channel effects such as Drain Induced Barrier lowering (DIBL) and threshold voltage roll-off have serious influences on the performance of devices. 11,12 Many structures have been proposed during last decade for single gate and multi gate structures that can reduce the short channel effects. 13,14 In this paper, a novel structure is proposed which can reduce the short channel effects. The new structure is based on extending the drain region into the channel which is called Extended Drain in the channel region of SOI MOSFET (ED-SOI). So, the drain region becomes larger and the channel region gets smaller. In this case, the carriers, which participate in the current, can pass from a direction with low resistance since the extended drain has...

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G4-FET modeling for circuit simulation by adaptive neuro-fuzzy training systems

Cited by 15 publications

References 11 publications

Reducing Floating Body and Short Channel Effects in Nano Scale Transistor: Inserted P⁺Region SOI-MOSFET

Reducing Floating Body and Short Channel Effects in Nano Scale Transistor: Inserted P⁺Region SOI-MOSFET

Analog performance investigation of misaligned double gate junctionless transistor

Improved Device Performance in Nano Scale Transistor: An Extended Drain SOI MOSFET

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G4-FET modeling for circuit simulation by adaptive neuro-fuzzy training systems

Cited by 15 publications

References 11 publications

Reducing Floating Body and Short Channel Effects in Nano Scale Transistor: Inserted P+Region SOI-MOSFET

Reducing Floating Body and Short Channel Effects in Nano Scale Transistor: Inserted P+Region SOI-MOSFET

Analog performance investigation of misaligned double gate junctionless transistor

Improved Device Performance in Nano Scale Transistor: An Extended Drain SOI MOSFET

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Product

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Reducing Floating Body and Short Channel Effects in Nano Scale Transistor: Inserted P⁺Region SOI-MOSFET

Reducing Floating Body and Short Channel Effects in Nano Scale Transistor: Inserted P⁺Region SOI-MOSFET