GaAs high‐k dielectric metal‐insulator‐semiconductor structure having silicon interface control layer

Akazawa, Masamichi; Hasegawa, Hideki

doi:10.1002/pssc.200779208

Cited by 2 publications

(2 citation statements)

References 8 publications

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“…A very similar result was also obtained on the air-exposed InGaAs surface after each step of processing, and this has been reported elsewhere in our preliminary study of formation of a HfO 2 /InGaAs structure [15].…”

Section: Thermal Cleaning and Mbe Growth Of Si Iclsupporting

confidence: 89%

High-k Al2O3 MOS structures with Si interface control layer formed on air-exposed GaAs and InGaAs wafers

Akazawa

Hasegawa

2010

Applied Surface Science

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This paper attempts to realize unpinned high-k insulator-semiconductor interfaces on air-exposed GaAs and In 0.53 Ga 0.47 As by using the Si interface control layer (Si ICL).Al 2 O 3 was deposited by ex-situ atomic layer deposition (ALD) as the high-k insulator.By applying an optimal chemical treatment using HF acid combined with subsequent thermal cleaning below 500 o C in UHV, interface bonding configurations similar to those by in-situ UHV process was achieved both for GaAs and InGaAs after MBE growth of the Si ICL with no trace of residual native oxide components.As compared with the MIS structures without Si ICL, insertion of Si ICL improved the electrical interface quality a great deal both for GaAs and InGaAs, reducing frequency dispersion of capacitance, hysteresis effects and interface state density (D it ). A minimum value of D it of 2x10 11 eV -1 cm -2 was achieved both for GaAs and InGaAs. However, the range of bias induced surface potential excursion within the band gap was different, making formation of electron layer by surface inversion possible in InGaAs, but not possible in GaAs. The difference was explained by the disorder induced gap state (DIGS) model.

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Section: Thermal Cleaning and Mbe Growth Of Si Iclsupporting

confidence: 89%

High-k Al2O3 MOS structures with Si interface control layer formed on air-exposed GaAs and InGaAs wafers

Akazawa

Hasegawa

2010

Applied Surface Science

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“…1͑c͒. 26,27 As for the semiconductor material, we stick to GaAs, although we are aware that InGaAs will give much better MIS interface properties 16 due to reduced energy distance between the band edge and the charge neutrality level, as we explained by the disorder induced gap state model 28 and recently confirmed also by Xuan et al 29 Thus, GaAs is a better material to test the effectiveness of a passivation technology for n-channel devices. For interface trap density ͑D it ͒ characterization, either the highfrequency method ͑often referred as Terman's method 20 ͒, typically using 1 MHz C-V curve as is done in Si MOS, or the low-frequency quasistatic capacitance method, is commonly used, ignoring the frequency dispersion taking place in between.…”

Section: Introductionmentioning

confidence: 97%

Admittance study of GaAs high-k metal-insulator-semiconductor capacitors with Si interface control layer

Akazawa¹,

Hasegawa²

2008

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inFabrication of ( NH 4 ) 2 S passivated GaAs metal-insulator-semiconductor devices using low-frequency plasmaenhanced chemical vapor deposition Si3N4/Si/In0.05Ga0.95As/n-GaAs metal-insulator-semiconductor devices Admittance behavior of high-k GaAs metal-insulator-semiconductor ͑MIS͒ capacitors having an ultrathin SiN x / Si interface control double layer has been investigated in detail. The measured admittance showed characteristic features that are difficult to explain by the standard Si metal-oxide-semiconductor theory. They include ͑1͒ vertical and horizontal types of frequency dispersion in C-V curves, ͑2͒ presence of offset conductance in G / -f plot, and ͑3͒ discrepancy between the surface potential from the high-frequency capacitance and the corresponding relaxation frequency of interface states. All of these features are tentatively explained in a unified manner by a new distributed pinning spot ͑DPS͒ model where the MIS interface consists of DPSs in addition to pinning-free regions. When the separation of pinning spots is small, the sample shows vertical type of frequency dispersion with almost bias-independent high-frequency capacitance corresponding to pinning near midgap. When pinning spots are widely separated, the C-V curves show horizontal type of frequency dispersion, each curve showing large capacitance variation with bias. This is due to flatband voltage shifts caused by effective interface state charge at the pinning spots. The pinning spot also gives rise to conductance offset. The discrepancy related to the relaxation frequency of interface states is explained by appearance of saddle points in the potential due to interaction between pinning spots and pinning-free region.

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GaAs high‐k dielectric metal‐insulator‐semiconductor structure having silicon interface control layer

Cited by 2 publications

References 8 publications

High-k Al2O3 MOS structures with Si interface control layer formed on air-exposed GaAs and InGaAs wafers

High-k Al2O3 MOS structures with Si interface control layer formed on air-exposed GaAs and InGaAs wafers

Admittance study of GaAs high-k metal-insulator-semiconductor capacitors with Si interface control layer

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