GaAs SOI FinFET: impact of gate dielectric on electrical parameters and application as digital inverter

Abstract

In this paper, a GaAs SOI (silicon on insulator) FinFET is proposed. A comparative study between proposed GaAs FinFET and conventional Si FinFET is presented. The effects of dielectric constant (k) of gate dielectric material on electrical parameters like channel potential, drain current, and I on /I off have been reported. Results show that as k raises, both I on /I off and channel potential increases. Again the impact of k on short channel effects (SCEs) has been investigated. TCAD results show that as k increases subthreshold swing (SS) improves, drain induced barrier lowering (DIBL) degrades, and V T roll off occur. The impacts of k on gate capacitance (C GG) and intrinsic delay (τ) have been presented and they increases as k increases. A digital CMOS inverter is implemented through proposed FinFET and the effect of k on its delay parameter is estimated. Results shows that average delay increase as k increases.