Gain-enhanced 132–160 GHz low-noise amplifier using 0.13 µm SiGe BiCMOS

Abstract

A 132 -160 GHz low-noise amplifier (LNA) in 0.13 mm SiGe BiCMOS technology is presented. The gain-boosting technique and 3D grounded-shielding structures have been employed to achieve higher gain with lower power consumption and silicon occupation. The experimental results show that the LNA with a chip area of 400 × 900 mm achieves gain of 21 dB with a 3 dB bandwidth of 28 GHz and noise figure of 8.5 dB at 145 GHz, with total DC power consumption of 14.5 mW.Introduction: In millimetre-wave receiver design, the low-noise amplifier (LNA) is a critical building block that amplifies the received signal and contributes most of the noise figure of the whole receiver. In most previous research, high-performance III -V compound semiconductors were generally utilised for millimetre-wave LNA design. In recent years, with the downscaling of silicon-based device size, its f T and f MAX are rapidly increasing and have been demonstrated to be competitive with those of the III -V compound semiconductors [1]. In addition, with the compatibility with baseband circuit and high-quality passive elements, the silicon-based technology shows the advantage for costeffective highly integrated system-on-chip (SoC). But with the increase of operation frequency, the performance of the circuit has been greatly affected by the lossy silicon substrate and the thin metal loss. Thus, it is a challenge to realise a high gain and low noise figure LNA beyond 100 GHz frequency since the currently available gain of single transistor at such high frequency range is still small. In this Letter, we present a 132 -160 GHz LNA in 0.13 mm SiGe BiCMOS technology. By a gain-boosting technique, the gain of each stage of the LNA has been increased by more than 38.5% and further improved noise performance and power consumption. To improve multi-stage stability and reduce the impact from parasitic effect, a 3D grounded-shielding structure is used. The results show that the LNA has 21 dB peak gain and 8.5 dB noise figure at 145 GHz while the power consumption is 14.5 mW.

A 125–143-GHz Frequency-Reconfigurable BiCMOS Compact LNA Using a Single RF-MEMS Switch

“…The proposed LNA was designed to feature a well-balanced gain and noise figure in both states at the expense of lower gain and higher P DC . Even so, its F compares well to or betters those of [1], [4], [5], which were optimized for low-noise performance.…”

“…Compared to the frequency-reconfigurable LNAs with two RF-MEMS switches [8], [9], it is more compact (because the bias and RF-MEMS circuits barely scale with frequency), and exhibits a simpler configuration and a lower P DC . It is also considerably more compact than the (notreconfigurable) LNAs in [1], [3] [5], [7], which operate at comparable frequencies. The proposed LNA was designed to feature a well-balanced gain and noise figure in both states at the expense of lower gain and higher P DC .…”

THz Direct Detector and Heterodyne Receiver Arrays in Silicon Nanoscale Technologies

“…Below f max, SiGe HBT and CMOS LNAs have provided typical noise figures in the range of 7-8.5 dB at 130-160 GHz and 11 dB at 245 GHz [42][43][44][45]. The SiGe HBT-based receivers operating beyond the device cut-off frequencies have shown noise figures of 38 dB at 380 GHz [46], 44 dB at 650 GHz, and 45 dB at 820 GHz [32,33], whereas the CMOS-integrated receivers have demonstrated noise figures ranging from 15 to 68 dB for frequencies from 240 to 650 GHz [47][48][49].…”

A K-band power amplifier in 0.18 μm CMOS process with slow-wave structure

“…In order to achieve high and flat gain at higher frequency, an improved gain-boosting technique is adopted in this amplifier design. [11] The schematic of proposed amplifier is shown in Figure 3. In our design, we take the microstrip line instead of Lg to get an accurate and area-efficient inductance.…”