Gap-free Processor Verification by S<sup>2</sup>QED and Property Generation

Devarajegowda, Keerthikumara; Fadiheh, Mohammad Rahmani; Singh, Eshan; Barrett, Clark; Mitra, Subhasish; Ecker, Wolfgang; Stoffel, Dominik; Kunz, Wolfgang

doi:10.23919/date48585.2020.9116515

Cited by 8 publications

(5 citation statements)

References 10 publications

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“…As future work, it would be valuable to extend our framework to consider variants of SQED that operate with more fully symbolic initial states [22], [23]. The challenge will be to identify how this can be done while guaranteeing no spurious counterexamples.…”

Section: Discussionmentioning

confidence: 99%

“…It is also applicable to post-silicon validation. SQED was extended to operate with symbolic initial states [22], [23] to overcome the potential limitations of BMC when unrolling the transition relation of a design starting in a concrete initial state.…”

Section: Related Workmentioning

confidence: 99%

“…Several approaches, including both formal and simulationbased approaches, exist for checking single-instruction (SI) correctness cf. [9], [23], [30]. Checking SI correctness is complementary to checking self-consistency using SQED and is also much more tractable.…”

Section: Related Workmentioning

confidence: 99%

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A Theoretical Framework for Symbolic Quick Error Detection

Lonsing,

Mitra,

Barrett

2020

Preprint

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Symbolic quick error detection (SQED) is a formal pre-silicon verification technique targeted at processor designs. It leverages bounded model checking (BMC) to check a design for counterexamples to a self-consistency property: given the instruction set architecture (ISA) of the design, executing an instruction sequence twice on the same inputs must always produce the same outputs. Self-consistency is a universal, designindependent property. Consequently, in contrast to traditional verification approaches that use design-specific assertions (often generated manually), SQED does not require a formal design specification or manually-written properties. Case studies have shown that SQED is effective on commercial designs and substantially improves design productivity. However, until now there has been no formal characterization of its bug-finding capabilities. We aim to close this gap by laying a formal foundation for SQED. We use a transition-system processor model and define the notion of a bug using an abstract specification relation. We prove the soundness of SQED, namely that any bug reported by SQED is in fact a real bug in the processor. Importantly, this result holds regardless of what the actual specification relation is. We next describe conditions under which SQED is complete, that is, what kinds of bugs it is guaranteed to find. We show that for a large class of bugs, SQED can always find a trace exhibiting the bug. Our results enable a rigorous understanding of SQED and its bug-finding capabilities and give insights on how to optimize implementations of SQED in practice.

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Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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A Theoretical Framework for Symbolic Quick Error Detection

Lonsing,

Mitra,

Barrett

2020

Preprint

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“…Noteworthy approaches that are based on model checking techniques are the OneSpin 360 DV RISC-V Verification App 19) and riscv-formal 20) . Recently, research approaches targeting RISC-V pipelined microarchitectures emerged that rely on formal methods and consider functional properties [27] as well as transient execution attacks [28]. However, formal verification methods should be complemented by simulation-based approaches due to their complexity and potential scalability issues.…”

Section: Risc-v Verificationmentioning

confidence: 99%

Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges

Herdt

Drechsler

2021

Sci. China Inf. Sci.

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Virtual prototypes (VPs) are crucial in today’s design flow. VPs are predominantly created in SystemC transaction-level modeling (TLM) and are leveraged for early software development and other system-level use cases. Recently, virtual prototyping has been introduced for the emerging RISC-V instruction set architecture (ISA) and become an important piece of the growing RISC-V ecosystem. In this paper, we present enhanced virtual prototyping solutions tailored for RISC-V. The foundation is an advanced open source RISC-V VP implemented in SystemC TLM and designed as a configurable and extensible platform. It scales from small bare-metal systems to large multi-core systems that run applications on top of the Linux operating system. Based on the RISC-V VP, this paper also discusses advanced VP-based verification approaches and open challenges. In combination, we provide for the first time an integrated and unified overview and perspective on advanced virtual prototyping for RISC-V.

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“…A-QED 2 builds on A-QED [8] and leverages BMC [11], [37]. Similar approaches based on self-consistency have been successfully applied to other classes of hardware designs, such as processor verification (as symbolic quick error detection (SQED) [38]- [43]), as well as to hardware security [44]- [49].…”

Section: Related Workmentioning

confidence: 99%

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Chattopadhyay,

Lonsing,

Piccolboni

et al. 2021

Preprint

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Hardware accelerators (HAs) are essential building blocks for fast and energy-efficient computing systems. Accelerator Quick Error Detection (A-QED) is a recent formal technique which uses Bounded Model Checking for pre-silicon verification of HAs. A-QED checks an HA for self-consistency, i.e., whether identical inputs within a sequence of operations always produce the same output. Under modest assumptions, A-QED is both sound and complete. However, as is well-known, large design sizes significantly limit the scalability of formal verification, including A-QED. We overcome this scalability challenge through a new decomposition technique for A-QED, called A-QED with Decomposition (A-QED 2 ). A-QED 2 systematically decomposes an HA into smaller, functional sub-modules, called sub-accelerators, which are then verified independently using A-QED. We prove completeness of A-QED 2 ; in particular, if the full HA under verification contains a bug, then A-QED 2 ensures detection of that bug during A-QED verification of the corresponding subaccelerators. Results on over 100 (buggy) versions of a wide variety of HAs with millions of logic gates demonstrate the effectiveness and practicality of A-QED 2 . This article will appear in the proceedings of Formal Methods in Computer-Aided Design (FMCAD 2021).

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Gap-free Processor Verification by S²QED and Property Generation

Cited by 8 publications

References 10 publications

A Theoretical Framework for Symbolic Quick Error Detection

A Theoretical Framework for Symbolic Quick Error Detection

Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

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Gap-free Processor Verification by S2QED and Property Generation

Cited by 8 publications

References 10 publications

A Theoretical Framework for Symbolic Quick Error Detection

A Theoretical Framework for Symbolic Quick Error Detection

Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

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Gap-free Processor Verification by S²QED and Property Generation