Gate-bias stress in amorphous oxide semiconductors thin-film transistors

Abstract

A quantitative study of the dynamics of threshold-voltage shifts with time in gallium-indium zinc oxide amorphous thin-film transistors is presented using standard analysis based on the stretched exponential relaxation. For devices using thermal silicon oxide as gate dielectric, the relaxation time is 3 ϫ 10 5 s at room temperature with activation energy of 0.68 eV. These transistors approach the stability of the amorphous silicon transistors. The threshold voltage shift is faster after water vapor exposure suggesting that the origin of this instability is charge trapping at residual-water-related trap sites. © 2009 American Institute of Physics. ͓DOI: 10.1063/1.3187532͔ Amorphous gallium-indium zinc oxide ͑GIZO͒ thin-film transistors ͑TFTs͒ have attracted attention for their possible applications to flat, flexible, and transparent displays, 1-4 especially when processed at low temperatures. However, like the other TFTs' technologies, they also suffer from a stability phenomena known as gate-bias stress. 5,6 This effect manifests itself as a continuous increase in threshold voltage ͑V th ͒ when the gate bias is kept constant over time. This limits the application of these TFTs in demanding applications, such as active matrix organic light emitting displays. The increase in V th lowers the luminance of individual pixels over time, causing display nonuniformity. 7 As an example, using current technologies several driving transistors per pixel are necessary to compensate for the V th shift. Hence, a proper understanding of the stressing mechanism is of paramount importance.Gate-bias stress effects are commonly reported in the literature for a variety of transistors, a-Si TFTs, 8 organic transistors, 9-11 and recently also in amorphous oxide semiconductors TFTs. [12][13][14][15] The effect has been explained as a slow trapping of charge carriers in defects of unknown origin located at the semiconductor/dielectric interface. 13 It is known that the current degradation is faster when the devices are exposed to atmosphere 15,16 and that the stability improves after annealing. 1 Also, it has been reported that the effects can be reduced by the insertion of a passivation layer, either between the dielectric and the semiconductor 17 or on top of the semiconductor in bottom-gate structures. 16 This work provides a quantitative study of the gate-bias stress instability as a function of temperature and environment conditions. The results allow a comparison with competing TFTs technologies. Furthermore, it also provides evidences that water vapor contamination enhances this instability. Therefore, there is no conceptual limitation for the stability of GIZO based TFTs. This is in contrast to hydrogenated amorphous silicon TFTs where the instability is caused by the creation of intrinsic defects, unsaturated valence states into which electrons are trapped.The device fabrication process has been described in detail elsewhere. 18 Briefly, the TFTs were produced with a staggered bottom gate configuration on silicon wafers, which a...

Undercoordinated indium as an intrinsic electron-trap center in amorphous InGaZnO4

“…A negatively charged deep level has been hypothesized to be created in experiments, accompanied by a positive shift of the threshold voltage. 20 The experimentally measured thermal activation energy for electron trapping (E a,trap ) is in the range of 0.22-0.95 eV [15][16][17][18][19]22 under PBS and 0.08-0.14 eV 20 under CS. The α energy barrier in the (In*-M) 2 − formation corresponds to these values, which vary depending on the carrier concentration (Figure 4b).…”

“…10 Thin-film transistors made of amorphous oxide semiconductors exhibit a variety of metastable changes in their transistor characteristics through carrier doping and optical [11][12][13] or electrical [14][15][16][17][18][19][20][21] (or both [21][22][23][24][25][26][27][28] ) excitation of carriers. Indium (In)-based amorphous oxide semiconductors are considered as a promising material for next-generation thin-film electronics and optoelectronics because they have high electron mobility, transparency, flexibility and uniformity.…”

“…In the range of n 4 10 20 cm − 3 , which is typical under PBS and CS conditions, the estimated α energy barriers are 0.0-1.4 eV in good agreement with the experiments (0.08-0.95 eV). [15][16][17][18][19][20]22 The thermal activation energy for electron detrapping (E a, detrap ) (after stopping the PBS or CS) has also been measured. This value can be interpreted as the β energy barrier in the (In*-M) 2 − → NS+2e − transition.…”

Operational stability of solution based zinc tin oxide/SiO2 thin film transistors under gate bias stress

“…In fact, even for high quality thermal SiO 2 typically used in test structures for performance evaluation of thin film semiconductors, it is not possible to assure an entirely perfect interface between dielectric and semiconductor. Previously, amorphous oxides using SiO 2 as dielectric suffer from a pronounced ∆V th , with time constants (τ) of 10 4 -10 5 s. 6,7,9 Here, we show evidences of intrinsically more stable solution-based zinc tin oxide (ZTO) TFTs from studying the time and temperature dependence of bias stress and recovering process. We propose that this enhanced stability is promoted by a defect passivation or neutralization of the SiO 2 surface and consequently reducing the number of traps.…”

Highly stable thin film transistors using multilayer channel structure

“…13 However, Kim et al 23 water assisted oxygen absorption lead to a significant V TH shift under PBS. 24 Further, it is believed that the adsorbed water molecules at the back channel can diffuse towards the channel/gate dielectric interface, 25 generating a large number of metastable gap states leading to a large number of trapped electrons and eventual increase in hole carrier density, and thus exhibiting larger negative DV TH under NBS. 13 The adsorbed oxygen concentration is believed to decrease at higher temperature leading to an increase in doubly charged oxygen vacancies (V O 2þ ) in the ZnO layer.…”