Gate bias temperature stress-induced off-state leakage in nMOSFETs: Mechanism, lifetime model and circuit design consideration

Modeling of the degradation of CMOS inverters under pulsed stress conditions from ‘on-the-fly’ measurements

“…When a low voltage (logic '0') is applied to the input (case A), a negative voltage drop between the gate-source and gate-drain terminals of the pMOSFET is forced, so that pMOSFET suffers NBTI stress. The nMOSFET is OFF, but a non-uniform electric field is applied to the gate dielectric, due to the large V DS forced by the '1' logic output, so that actually the nMOSFET suffers OFF-state aging [14][15][16][17][18][19]. It must be emphasized that usually this stress mode is overlooked in stand-alone device reliability tests, but it is actually acting in an inverter.…”

“…However, device aging in a circuit may differ from that actually experienced in this kind of tests. As an example, interestingly, for example, the relevance of off-state degradation [14][15][16][17][18][19] is not revealed. Other works analyze the sequential effect of several aging mechanisms by applying pulsed stress conditions, which are closer to circuit operation.…”