2023
DOI: 10.1109/ted.2023.3244765
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Gate-Controlled LVTSCR for High-Voltage ESD Protections in Advanced CMOS Processes

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Cited by 10 publications
(2 citation statements)
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“…In the forward conduction mode of the proposed device, Q P4 also contributes to the current flow as a parallel path. This leads to the holes of through the base region of the Q P1 are partly diverted by the Q P4, resulting in a decrease in the current gain of Q P1 [21]. Due to the reduction in minority carriers in P-Well (2), a higher current is required to trigger the inherent SCR.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…In the forward conduction mode of the proposed device, Q P4 also contributes to the current flow as a parallel path. This leads to the holes of through the base region of the Q P1 are partly diverted by the Q P4, resulting in a decrease in the current gain of Q P1 [21]. Due to the reduction in minority carriers in P-Well (2), a higher current is required to trigger the inherent SCR.…”
Section: Resultsmentioning
confidence: 99%
“…Recently, Chen et al proposed a gate-controlled low-voltage-triggered SCR (LVTSCR) device, adding a surface current conduction path in the device. By adjusting the bias voltage of the gate, the V h of the device can be improved [21]. However, the device's I t2 is only 1.31 A.…”
Section: Introductionmentioning
confidence: 99%