2022 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe) 2022
DOI: 10.1109/wipdaeurope55971.2022.9936342
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Gate-damage safe failure-mode deep analysis under short-circuit operation of 1.2kV and 1.7kV power SiC MOSFET using dedicated gate-source / drain-source voltage depolarization and damage-mode optical imaging

Abstract: Robustness of 1.2kV and 1.7kV Silicon Carbide MOSFETs submitted to short-circuit operations mode is studied. Experimental results confirm two main failure modes: a safe fail-to-open mode and an unsafe fail-to-short mode. A technique based on direct depolarization of gate source voltage is used to increase the short-circuit withstand capability and to partially obtain a fail-to-open mode. Electro-thermometallurgical simulations are investigated to deeply explain the fail-to-open mechanisms. Finally, using lock-… Show more

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Cited by 2 publications
(2 citation statements)
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“…In addition to improvements in chip architecture design, another approach consists in functionalising the gate-driver to efficient shortcircuit / over-current handling and dedicated gateoxide health monitoring -conditioning strategies. Among the previous work of the authors on discrete 1.2kV and 1.7kV SiC power MOSFETs, it was shown in [3] [4] that the reduction of the short-circuit power density to 4kW/mm² made it possible to exceed the threshold of 10µs short-circuit withstand time capability (TSCW) and to bring the chip to a safe gatesource short and drain-source open failure mode (Failto-Open FTO mode). Other authors have confirmed this property [5].…”
Section: Background Previous Work and Contributionmentioning
confidence: 99%
See 1 more Smart Citation
“…In addition to improvements in chip architecture design, another approach consists in functionalising the gate-driver to efficient shortcircuit / over-current handling and dedicated gateoxide health monitoring -conditioning strategies. Among the previous work of the authors on discrete 1.2kV and 1.7kV SiC power MOSFETs, it was shown in [3] [4] that the reduction of the short-circuit power density to 4kW/mm² made it possible to exceed the threshold of 10µs short-circuit withstand time capability (TSCW) and to bring the chip to a safe gatesource short and drain-source open failure mode (Failto-Open FTO mode). Other authors have confirmed this property [5].…”
Section: Background Previous Work and Contributionmentioning
confidence: 99%
“…3a, a power density reduction is provided by the proposed gate-driving architecture, thus allowing to avoid a thermal runaway. The gate region's thermomechanical stress is then the phenomenon governing the chip's main failure mechanism [4][5] should no protection be used or if repetitive shorts are applied [12]. Fig.…”
Section: Application To Gate-oxide Damage Monitoring and Detectionmentioning
confidence: 99%