Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits

Morgenshtein, Arkadiy; Fish, Alexander; Wagner, Israel A.

doi:10.1109/tvlsi.2002.801578

Cited by 299 publications

(112 citation statements)

References 17 publications

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“…Though we highlighted an "Optical Circuit" for information processing and computation of even/odd parity circuit, we are not discussing in detail as such advanced topics like Photonics and Optical Computing, which deserve another research paper on an in-depth basis. Hence we are of the belief that our current research work is one of the pioneering efforts in this promising domain of Branching Programs which is interdisciplinary in nature (Mehlhorn & Nher, 1995;Moreinis, Morgenshtein, Wagner, & Kolodny, 2006;Morgenshtein, Fish, & Wagner, 2002;Morgenshtein, Friedman, Ginosar, & Kolodny, 2008;Nakano & Wada, 1998;Nishihara, Haruna, & Suhara, 1987;Okayama, Okabe, Kamijoh, & Sakamoto, 1999;Reed & Knights, 2004;Shi, Wa, Miller, Pamulapati, & Cooke, 1995;Isabelle, 2012;Anthony Fox, 2012; HOL: The Higher Order Logic Theorem Prover; Barrington's Theorem, 2009).…”

Section: Discussionmentioning

confidence: 99%

“…One can have similar branching programs for the parity function. It can be shown that every function on n bits can be computed by a branching program of width 3 and exponential length" (Hunsperger, 2002;Hussein, Nounou, Saada, Atef, & Khalil, 2006;Jang, Park, & Prasanna, 1992;Taki, 2000;Lattner, 2002;Mehlhorn & Nher, 1995;Moreinis, Morgenshtein, Wagner, & Kolodny, 2006;Morgenshtein, Fish, & Wagner, 2002;Morgenshtein, Friedman, Ginosar, & Kolodny, 2008;Nakano & Wada, 1998;Nishihara, Haruna, & Suhara, 1987;Okayama, Okabe, Kamijoh, & Sakamoto, 1999;Reed & Knights, 2004;Shi, Wa, Miller, Pamulapati, & Cooke, 1995;Isabelle, 2012;Anthony Fox, 2012; HOL: The Higher Order Logic Theorem Prover; Barrington's Theorem, 2009). Figure 1, we designed a simple boolean circuit and deduced its equivalent branching program, using the established mathematical and computational paradigms.…”

Section: Branching Program/s (Bp)mentioning

confidence: 99%

See 1 more Smart Citation

A General Computational Framework and Simulations of Branching Programs of Boolean Circuits Using Higher Order Logic (HOL) Software - An Insight into ECAD Tool Design Paradigm

D.N.T.Kumar¹,

Wei²

2012

CIS

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Integrated optics and Optical computing are now a mature technology offering many types of devices and manufacturing techniques. Recent breakthroughs in the field of silicon photonics showed low-loss insulators, passive wave guide devices, high speed optical switches, detectors, silicon lasers, and silicon amplifiers, optical amplifiers etc. These devices have provided the possibility to construct CMOS compatible optical circuits with low power consumption, high bandwidth and low latencies. A critical component that we intend to focus is on considering Branching Programs as CAD tools for the design of future electronics. Hence, BPs as viable means to accomplish the task of propelling the R&D of Electronics, are considered and simulated using HOL software based on boolean theory. We believe our research is one of the remarkable pioneering efforts, into the promising aspects of Branching Programs as CAD Tools.

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Section: Discussionmentioning

confidence: 99%

Section: Branching Program/s (Bp)mentioning

confidence: 99%

A General Computational Framework and Simulations of Branching Programs of Boolean Circuits Using Higher Order Logic (HOL) Software - An Insight into ECAD Tool Design Paradigm

D.N.T.Kumar¹,

Wei²

2012

CIS

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“…It looks like CMOS inverter but the source and drain input of both the transistors are different [13] - [15].…”

Section: Gdi Techniquementioning

confidence: 99%

Efficient Design of 1- bit Low Power Full Adder using GDI Technique

2017

IJSR

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Abstract:The two important issues in designing of analog circuits are area and power which can be controlled by various parameters.Addition is one of the important mathematical operations which serve as a building block. A low power full adder is the important circuit in the designing of other large circuits. In this paper, three low power full adders are designed using basic gate OR, AND, XOR and XNOR. These gates are designed by using GDI technique. When the number of transistors are decreased then the power consumption and area is reduced.GDI is a new technique for low power digital circuits .This techniques reduce the power consumption, propagation delay and transistor count of digital circuits. The adder cell consists of XOR and XNOR gates. The performance of different adder is compared in respect of various parameters. From results, its cleared that the due to less transistor count the power consumption and area is reduced DSCH and MICROWIND tool is used for the circuit design and simulation of it.

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“…To reduce the area and power various techniques are used. Some of them are CMOS, Transmission Gate [1], Pass Transistor logic [1] etc. Although these several techniques have been proposed to reduce the area, power consumption but there were some limitations like low logic level and circuit complexity in it.…”

Section: Introductionmentioning

confidence: 99%

“…Step: 1 step: 2 1101(13) 1001(9) +1011 (ones complement of 4) +1011 11000 10100 1 1 1001 (9) 0101 (5) Step: 3 step: 4 0101(5) 0001(1) +1011 +1011 10000 01100 1 -0011(-3) 0001 (1) carry is zero Here when difference is positive final carry is 1 which is end around and added to get the actual difference. When difference is negative, carry is zero and true result is obtained by one's complement of the sum output.…”

Section: Introductionmentioning

confidence: 99%

Serial Divider Using Modified GDI Technique

A.S.¹,

Naveena²,

Parimaladevi³

et al. 2015

International Journal of Innovative Research in Electrical, Ele

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Divider is a basic hardware module in advanced and high speed digital signal processing (DSP) units. It has the applications in radar technology, communication, industrial control systems and linear predictive coding (LPC) algorithms in speech processing. This paper presents 4-bit Serial Divider using Modified GDI Technique. The repeated one's complement method of binary subtraction algorithm is used for serial division. The proposed method aims on Modified Gate Diffusion Input (mod-GDI) which is a low power technique to design any digital system. This technique has been adopted from Gate Diffusion Input (GDI).The Modified GDI technique which allows in reducing delay, power consumption and area compared to conventional CMOS Technology. According to the estimations done, the transistor count, Tool analysis time, power consumption of serial divider using CMOS technology and the Modified GDI technique is tabulated. The designs are simulated using the Tanner EDA tool.

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Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits

Cited by 299 publications

References 17 publications

A General Computational Framework and Simulations of Branching Programs of Boolean Circuits Using Higher Order Logic (HOL) Software - An Insight into ECAD Tool Design Paradigm

A General Computational Framework and Simulations of Branching Programs of Boolean Circuits Using Higher Order Logic (HOL) Software - An Insight into ECAD Tool Design Paradigm

Efficient Design of 1- bit Low Power Full Adder using GDI Technique

Serial Divider Using Modified GDI Technique

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