Gate Diffusion Input technique based full swing and scalable 1-bit hybrid Full Adder for high performance applications

Hasan, Mehedi; Zaman, Hasan U.; Hossain, Mainul; Biswas, Parag; Islam, Sharnali

doi:10.1016/j.jestch.2020.05.008

Cited by 44 publications

(20 citation statements)

References 21 publications

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“…As per Table 2, the proposed design accomplished 4.84 % improvement in power consumption. Dynamic power in integrated circuit is the major contributor to the overall power consumption which occurs due to transitions of logic gates [16][17][18]. The proposed 4-bit CLA adder reduced dynamic power by completely eliminating the AND gates (G i terms) from the design.…”

Section: Simulation Results Analysis and Comparisonmentioning

confidence: 99%

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Hasan

Siddique

Mondol

et al. 2020

IJEEI

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Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.

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Section: Simulation Results Analysis and Comparisonmentioning

confidence: 99%

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Hasan

Siddique

Mondol

et al. 2020

IJEEI

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“…Logic implementation using the GDI technique can be realized from [61], where basic logic gates using the GDI technique, have been presented. The major issue regarding GDI methodbased circuit is its voltage degradation which reduces drive capability significantly [62]. Several FAs employing the GDI technique have been developed for low-power applications which require less surface area due to low TC [63].…”

Section: Hybrid Logic Full Addersmentioning

confidence: 99%

Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis

et al. 2021

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Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units (ALUs) of modern computing systems. Recently, there have been massive research interests in this area due to the growing need for low-power and high-performance computing systems. Researchers have proposed a variety of FA cells with diverse design techniques, each having its pros and cons. As a result, a systematic method for performance comparison of FA cells using a common simulation platform has become necessary. In this work, we present an extensive study of FA cells. We have compared the performance of thirty-three (33) existing 1-bit FA cells. The drive powers of these FA cells have been compared by applying a variety of load conditions. In addition, the 1-bit FA cells have been extended to 32-bit structures to test their scalability and to investigate their performance in wide-word structures. We have determined that twenty-one (21) of the thirty-three (33) FA cells cannot operate in a 32-bit structure, even though some of them exhibit excellent performance as a 1-bit cell. The main finding of this research is that the single-bit performance parameters of FA cells should not be considered as the main basis for performance comparison. Any FA cell should be analyzed in a multi-bit structure to determine its practical effectiveness.

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“…A common simulation setup for all FA circuits is required for a fair comparison. This research followed the simulation setup presented in [14,17]. Signals in microprocessors pass through several circuit components which create signal distortions.…”

Section: Simulation Setup and Performance Parametersmentioning

confidence: 99%

A high‐performance full swing 1‐bit hybrid full adder cell

Hussain

Hasan

Agrawal

et al. 2021

IET Circuits, Devices & Syst

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This study proposes an 18-transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR-XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has been carried out using an HSPICE simulator at the 16 nm process node by comparing it with eight existing FAs over the supply voltage ranging from 0.4 to 1.0 V. The proposed adder achieved 34.77% improvement in propagation delay, 48.8% improvement in average power and 66.58% improvement in Power Delay Product compared to the conventional CMOS Mirror adder while operating at 0.8 V. Moreover, its performance metrics are also better than those of other latest existing adder cells. Hence, the proposed FA is suitable for modern high performance digital processors.

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Gate Diffusion Input technique based full swing and scalable 1-bit hybrid Full Adder for high performance applications

Cited by 44 publications

References 21 publications

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis

A high‐performance full swing 1‐bit hybrid full adder cell

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