Gate-first high-k/metal gate DRAM technology for low power and high performance products

Sung, Minchul; Jang, Se-Aug; Lee, Hyunjin; Ji, Yunhyuck; Kang, Jae-Il; Jung, Tae-O; Ahn, Tae Ho; Son, Yunik; Kim, Hyung Chul; Lee, Sunwoo; Lee, Seung-Mi; Lee, Jung-Hak; Baek, Seung-Beom; Doh, Eun-Hyup; Cho, Heung-Jae; Jang, T.; Jang, Ilsik; Han, Jizhong; Ko, K.; Lee, Yu-Jun; Shin, Su-Bum; Yu, Jae-Seon; Cho, Sung-Hyuk; Han, Jin−Woo; Kang, Dongkyun; Kim, Jin-Sung; Lee, Jaesang; Ban, Keundo; Yeom, Seung Jin; Nam, Hyunwook; Lee, Dong‐Kyu; Jeong, Mun-Mo; Kwak, B.S.; Park, Jeongsoo; Choi, Kwang-Il; Park, Sung-Kye; Kwak, Noh-Jung; Hong, Sung-Joo

doi:10.1109/iedm.2015.7409775

Cited by 17 publications

(2 citation statements)

References 4 publications

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“…12,13) Therefore, Gate First integration seems more suitable for Memory application, and its feasibility has been proved by different teams. [14][15][16] After the planar HKMG, the next generation DRAM memories will require additional power-performance-areacost benefit, forcing the transition to a FinFET based platform offering additional power and performance benefit without adding significant cost. 17) In this work we have investigated the fabrication of FinFET devices specifically tailored for memory application, by extending the finding shown in Ref.…”

Section: Introductionmentioning

confidence: 99%

80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications

Spessot¹,

Ritzenthaler²,

Litta³

et al. 2021

Jpn. J. Appl. Phys.

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Automotive, Artificial Intelligence/Machine Learning and blockchain generation are imposing increasing demanding specs for Dynamic Random Access Memory (DRAM) memories. Wider memory bandwidth can be achieved by using conventional planar SiO2 MOSFET and different interfaces but at the expense of required energy per bit. Advantages of High-K/Metal Gate versus SiO2/SiON planar DRAM periphery devices compatible with DRAM memory fabrication have been demonstrated in literature. More recently, the power performance benefit of FinFET for DRAM peri devices have been discussed. In this paper we provide a detailed analysis and additional insights in the first experimental validation of a thermally stable, reliable and cost effective tall fins platform (65 and 80 nm fin height). Power performance benefit versus fin height and expected area advantages on Sense Amp area are presented.

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Section: Introductionmentioning

confidence: 99%

80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications

Spessot¹,

Ritzenthaler²,

Litta³

et al. 2021

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

show abstract

“…For the memory side, the scaling of device footprint enabled a higher memory density ( Hwang, 2002 ). However, extensive scaling led to many challenges, which were overcome by the memory industry with process innovations such as higher aspect ratio of DRAM, and material innovations like high-k materials ( Mueller et al, 2005 ; Sung et al, 2015 ; Jang et al, 2019 ). For the interconnect side, the transistor scaling has been also a key enabler for a higher bandwidth, because a faster transistor makes a circuit faster ( Daly, Fujino & Smith, 2018 ; Horowitz, Yang & Sidiropoulos, 1998 ).…”

Section: Introductionmentioning

confidence: 99%

Today’s computing challenges: opportunities for computer hardware design

Bae

2021

PeerJ Computer Science

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Due to the explosive increase of digital data creation, demand on advancement of computing capability is ever increasing. However, the legacy approaches that we have used for continuous improvement of three elements of computer (process, memory, and interconnect) have started facing their limits, and therefore are not as effective as they used to be and are also expected to reach the end in the near future. Evidently, it is a large challenge for computer hardware industry. However, at the same time it also provides great opportunities for the hardware design industry to develop novel technologies and to take leadership away from incumbents. This paper reviews the technical challenges that today’s computing systems are facing and introduces potential directions for continuous advancement of computing capability, and discusses where computer hardware designers find good opportunities to contribute.

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Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling

et al. 2022

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Processing-in-Memory (PIM) has been actively studied to overcome the memory bottleneck by placing computing units near or in memory, especially for efficiently processing low locality dataintensive applications. We can categorize the in-DRAM PIMs depending on how many banks perform the PIM computation by one DRAM command: per-bank and all-bank. The per-bank PIM operates only one bank, delivering low performance but preserving the standard DRAM interface and servicing non-PIM requests during PIM execution. The all-bank PIM operates all banks, achieving high performance but accompanying design issues like thermal and power consumption. We introduce the memory-computation decoupling execution to achieve the ideal all-bank PIM performance while preserving the standard JEDEC DRAM interface, i.e., performing the per-bank execution, thus easily adapted to commercial platforms. We divide the PIM execution into two phases: memory and computation phases. At the memory phase, we read the bank-private operands from a bank and store them in PIM engines' registers bank-by-bank. At the computation phase, we decouple the PIM engine from the memory array and broadcast a bank-shared operand using a standard read/write command to make all banks perform the computation simultaneously, thus reaching the computing throughput of the all-bank PIM. For extending the computation phase, i.e., maximizing all-bank execution opportunity, we introduce a compiler analysis and code generation technique to identify the bank-private and the bank-shared operands. We compared the performance of Level-2/3 BLAS, multi-batch LSTM-based Seq2Seq model, and BERT on our decoupled PIM with commercial computing platforms. In Level-3 BLAS, we achieved speedups of 75.8x, 1.2x, and 4.7x compared to CPU, GPU, and the per-bank PIM and up to 91.4% of the ideal all-bank PIM performance. Furthermore, our decoupled PIM consumed less energy than GPU and the per-bank PIM by 72.0% and 78.4%, but 7.4%, a little more than the ideal all-bank PIM.INDEX TERMS Memory-computation decoupling, in-memory processing, standard memory interface, all-bank execution.

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Gate-first high-k/metal gate DRAM technology for low power and high performance products

Cited by 17 publications

References 4 publications

80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications

80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications

Today’s computing challenges: opportunities for computer hardware design

Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling

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