Gate Leakage Impact on Full Open Defects in Interconnect Lines

Arumí, D.; Rodríguez-Montañés, R.; Figueras, Joan; Eichenberger, S.; Hora, C.; Kruseman, B.

doi:10.1109/tvlsi.2010.2077315

Cited by 8 publications

(10 citation statements)

References 31 publications

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“…The faulty line voltage depends on the surroundings, the capacitances of the driven gates, and on the initial trapped charge, as reported in previous works [4]- [12]. Furthermore, it has been recently Manuscript demonstrated that gate leakage currents also affect the behavior of faulty lines due to interconnect full open defects in nanometer technologies [13]- [16]. The logic interpretation of the faulty line due to an interconnect open depends on the logic input threshold voltages of the downstream gates for each particular test pattern.…”

Section: Introductionmentioning

confidence: 59%

“…The points represent the voltage difference due to the influence of gate leakage currents between two consecutive patterns (including the scan vectors). The dotted lines correspond to the predicted B IG(VDD) and B IG(GND) bounds according to the simplified expressions (15) and (16). It is observed how B IG(VDD) and B IG (GND) act, in fact, as a lower and a upper bound, respectively.…”

Section: F Simplification Of Gate Leakage Charge Bounds Computationmentioning

confidence: 94%

“…Gate leakage currents may induce a transient behavior on the faulty node until the steady-state voltage is reached [13]- [16]. The exact behavior depends on the initial FNV.…”

Section: B Simulation and Experimental Evidence Of The Faulty Node Bmentioning

confidence: 99%

See 2 more Smart Citations

Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents

Arumí

Rodríguez-Montañés

Figueras

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Accurate diagnosis of open defects is key to identifying process problems and achieving fast yield improvement. Current diagnosis methodologies for interconnect full open defects have demonstrated their efficiency, assuming that the defective line voltage is mainly determined by neighboring lines and downstream transistor parasitic capacitances. However, the continuous reduction of oxide thickness with every technology node increases gate leakage current significantly, even for highk dielectrics. In this context, in nanometer CMOS technologies, the defective line cannot be assumed to be electrically isolated because of the impact of gate leakage currents, which may invalidate diagnosis results provided by present methodologies. In this paper, a new methodology is proposed to diagnose interconnect full open defects under the influence of gate leakage currents in CMOS technologies.To the authors' knowledge, such influence has not been previously considered by any of the existing methodologies. Simulation and experimental results demonstrate the proposal efficiency.

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Section: Introductionmentioning

confidence: 59%

Section: F Simplification Of Gate Leakage Charge Bounds Computationmentioning

confidence: 94%

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Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents

Arumí

Rodríguez-Montañés

Figueras

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The exact influence depends on the relationship between the capacitances undergoing a rising (falling) transition or remaining at a constant value. The faulty node behaves similar to an interconnect line affected by a full open [22]- [25]. The difference lies in that the faulty node is in a high impedance state for some specific excitations whereas the interconnect line affected by a full open always remains disconnected from the driver.…”

Section: B Influence Of Downstream Parasitic Capacitancesmentioning

confidence: 99%

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

Arumí

Rodríguez-Montañés

Figueras

2016

IEEE Trans. VLSI Syst.

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Abstract-Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies.

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“…The electrical behavior of the floating node is determined by the neighborhood capacitances to the defective floating node, the transistor gate charge, and the charges trapped at the floating line [4]- [6]. Recently, it has been found that the gate tunneling leakage may influence the interconnect open behavior in some technologies [7], but this effect is not considered in this brief. Manuscript Detectability conditions as well as test generation methods for interconnect opens have been proposed in [6] and [8]- [11].…”

Section: Introductionmentioning

confidence: 98%

Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations

Moreno

Renovell

Champac

2016

IEEE Trans. VLSI Syst.

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Interconnect opens are a major class of defects found in today's nanometer technologies. These defects present subtle behavior that could lead to test escapes and hence compromise test quality. Furthermore, they could become a reliability risk. Low-voltage testing has been suggested as a static test to improve the defect coverage of interconnect opens. In nanometer technologies, process variability is predominant and considering only the nominal value of parameters is not realistic. Hence, process variations should be considered to analyze the behavior of interconnect opens. In this brief, the detection capabilities of low-voltage testing for interconnect opens considering process variations is investigated. A statistical model is used for the interconnect open defect. Correlation between parameters of the affected gates and spatial correlation of the parameters for those gates tied to the defective floating node have been considered. The proposed methodology is implemented in a software tool to determine the probability of detection of via opens for some ISCAS85 benchmark circuits. Based on these results, it is suggested to use low V DD in conjunction with favorable logic conditions at the coupling lines to enhance the defect coverage of interconnect opens leading to better test quality and higher product reliability.

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Gate Leakage Impact on Full Open Defects in Interconnect Lines

Abstract: Abstract-An

Cited by 8 publications

References 31 publications

Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents

Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations

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