Gate-length biasing for runtime-leakage control

Abstract

Abstract-Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques increase the leakage power and, therefore, causes its share of total power to increase. Manufacturers face the additional challenge of leakage variability: Recent data indicate that the leakage of microprocessor chips from a single 180-nm wafer can vary by as much as 20×. Previously proposed techniques for leakage-power reduction include the use of multiple supply and gate threshold voltages, and the assignment of input values to inactive gates, such that leakage is minimized.The additional design space afforded by the biasing of device gate lengths to reduce chip leakage power and its variability is studied. It is well known that leakage power decreases exponentially and delay increases linearly with increasing gate length. Thus, it is possible to increase gate length only marginally to take advantage of the exponential leakage reduction, while impairing performance only linearly. From a design-flow standpoint, the use of only slight increases in gate length preserves both pin and layout compatibility; therefore, the authors' technique can be applied as a postlayout enhancement step. The authors apply gate-length biasing only to those devices that do not appear in critical paths, thus assuring zero or negligible degradation in chip performance. To highlight the value of the technique, the multithreshold voltage technique, which is widely used for leakage reduction, is first applied and then gate-length biasing is used to show further reduction in leakage.Experimental results show that gate-length biasing reduces leakage by 24%-38% for the most commonly used cells, while incurring delay penalties of under 10%. Selective gate-length biasing at the circuit level reduces circuit leakage by up to 30% with no delay penalty. Leakage variability is reduced significantly by up to 41%, which may lead to substantial improvements in the manufacturing yield and the product cost. The use of gate-length biasing for leakage optimization of cell instances is also assessed, in which: 1) not all timing arcs are timing critical and/or 2) the rise and fall transitions are not both timing critical at the same time.

Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors

“…The slack of cell c is defined as the minimum slack on any timing arc containing c. The power of cell c is the sum of static power (w stat (c)) and dynamic power (w dyn (c)) for the cell. This formulation of sensitivity is similar to those proposed by previous works targeting leakage power reduction [13,14]. Select path p from P with maximum toggle rate; 4. for each cell c in path p do 5. if c.visited == true then continue; 6. c.visited ← true;…”

“…Sensitivity-based downsizing approaches have been proposed in [10], [24], [25], [15], [13], and [14]. TILOS [10] proposes a heuristic that sizes transistors iteratively, according to the sensitivity of the critical path delay to the transistor sizes, in order to find an optimum (with maximum delay reduction / transistor width increase).…”

“…The techniques proposed in [13] and [14] use sensitivity-based downsizing (i.e., begin with all nominal cell variants and replace cells on non-critical paths with long channel-length variants) heuristics for leakage optimization.…”

“…The sensitivities are computed for all cell instances. The heuristics of [13], [14] select a cell with the largest sensitivity and perform downsizing with a logically equivalent cell. If there is no timing violation in incremental STA, this move is accepted and saved.…”

Statistical Timing and Power Optimization of Architecture and Device for FPGAs

“…Cheng et al [2008] presented a framework to estimate the power, delay, variation, and reliability for FPGAs. Gupta et al [2006] applied gate-length biasing in the critical path to assure zero or negligible degradation in chip performance. Babaa et al [2006] mitigated the effect of the variations and provided a better leakage yield by either speeding up the slow blocks or slowing down the leaky ones.…”