Gate sizing and buffer insertion using economic models for power optimization

Murugavel, Ashok K.; Ranganathan, N.

doi:10.1109/icvd.2004.1260924

Cited by 13 publications

(10 citation statements)

References 12 publications

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“…In the pioneering work on process variations by Sani Nassif [37], it has been pointed out that in the absence of real statistical data on a process run it's reasonable to assume a variation parameter value of 25% on the delay due to process variations. The uncertainty in the delay values are transferred to the coefficients and of the linear delay model shown in (6). Following the above assumption, in the work reported in [16] and [17], it has been pointed out that the regression coefficients and closely approximate the variation effects of and based on simulation experiments with statistical data.…”

Section: B Variation Modeling With Spatial Correlationmentioning

confidence: 97%

“…Hence, the path based formulation is converted to a node based optimization problem [16], [17]. The node based formulation is a widely used technique [3], [6], [7], [11], [16], [17] to improve the computational efficiency of optimizing large circuits. The gate sizing problem with the node based formulation can be shown as s.t.…”

Section: Variation Aware Fuzzy Gate Sizingmentioning

confidence: 99%

“…Secondly, in this work we model gate delay as a linear function of gate size. The linear delay model proposed in [30] is given by (6) where refers to the size of gate , is the set of gates that fan out from gate , constant coefficients , , are empirically determined by extensive SPICE simulations for each gate in the library for various sizes and fanout counts. A similar nominal delay model has also been used in a recent stochastic programming based statistical gate sizing approach [17].…”

Section: A Power and Timing Modelsmentioning

confidence: 99%

See 2 more Smart Citations

A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing

Mahalingam

Ranganathan

Harlow

2008

IEEE Trans. VLSI Syst.

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Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact on the yield of the integrated circuits and need to be considered early in the design flow. Traditional corner based deterministic methods are no longer effective and circuit optimization methods require reinvention with a statistical perspective. In this paper, we propose a new gate sizing algorithm using fuzzy linear programming in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay which is a function of the gate sizes and the fan-outs of the gates are represented using triangular fuzzy numbers with linear membership functions. Initially, as a preprocessing step for fuzzy optimization, we perform deterministic optimizations by fixing the fuzzy parameters to the worst and the average case values, the results of which are used to convert the fuzzy optimization problem into a crisp nonlinear problem. The crisp problem with delay and power as constraints is then formulated to maximize the robustness, i.e., the variation resistance of the circuit. The fuzzy optimization approach was tested on ITC'99 benchmark circuits and the results were validated for timing yield using Monte Carlo simulations. The proposed approach is shown to achieve better power reduction than the worst case deterministic optimization as well as the stochastic programming based gate sizing methods, while having comparable runtimes.

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Section: B Variation Modeling With Spatial Correlationmentioning

confidence: 97%

Section: Variation Aware Fuzzy Gate Sizingmentioning

confidence: 99%

Section: A Power and Timing Modelsmentioning

confidence: 99%

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A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing

Mahalingam

Ranganathan

Harlow

2008

IEEE Trans. VLSI Syst.

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“…Transistor stacking [9], which is based on the fact that two transistors stacked in series in off-mode exhibit less leakage current than one transistor with the double channel length, has been shown to be able to reduce leakage. Gate sizing and buffer insertion [15] has also accepted a lot of attention both for deterministic and statistical delay and power optimization.…”

Section: Introductionmentioning

confidence: 99%

Statistical Timing-Based Post-Placement Leakage Recovery

Kounalakis

Sotiriou

Zebilis

2011

2011 IEEE Computer Society Annual Symposium on VLSI

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This work presents a post-placement, leakagerecovery methodology, based on gate resizing, which supports and preserves statistical constraints, i.e. a (mean, sigma) constraint pair during leakage optimization. We exploit statistical models for delay and leakage, which utilize normal and lognormal distributions respectively. The distributions are extracted by extrapolating process, temperature and voltage data. Our leakagerecovery is based on statistical wire delay bounds generated for a (sigma, mean) constraint by the TSZSA algorithm and redistributed across gates using an ILP-based slack reassignment strategy. Available gate slack is converted into reduced leakage by downsizing the relevant gates, while preserving the statistical slack assignment. Experimental results, on the IWLS 2005 benchmarks, indicate an average of over %20 leakage recovery with no timing yield loss, where similar leakage gains for a non-statistical, state of the art leakage recovery tool present an average of over %6 loss in timing yield. We also illustrate that our gate resizing algorithm exploits a delay-leakage trade off, for a fixed sigma value.

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“…In distributed embedded software [9], buffering techniques are employed to achieve effective communication among asynchronous processes. In VLSI domain, buffer insertion has been in use for power optimization, by reducing switched capacitance, and for synchronizing hardware modules [10].…”

Section: Related Workmentioning

confidence: 99%

Communication minimization for in-network processing in body sensor networks: A buffer assignment technique

Ghasemzadeh¹,

Jain²,

Sgroi³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Body sensor networks are emerging as a promising platform for healthcare monitoring. These systems are composed of battery-operated embedded devices which process physiological data. The reduction in the power consumption is an important factor to increase the lifetime for such systems and to enhance their wearability through reducing the size of the battery. In this paper, we develop an energy-efficient communication scheme that uses buffers to reduce the number of transmissions among the sensor nodes constrained to limited hardware resources. A direct acyclic graph is used to model the information flow. We define a communication optimization problem and solve it using convex optimization techniques. We present results that support the efficiency of the proposed technique.

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Gate sizing and buffer insertion using economic models for power optimization

Cited by 13 publications

References 12 publications

A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing

A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing

Statistical Timing-Based Post-Placement Leakage Recovery

Communication minimization for in-network processing in body sensor networks: A buffer assignment technique

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