Gate sizing in MOS digital circuits with linear programming

Berkelaar, M.R.C.M.; Jess, J.A.G.

doi:10.1109/edac.1990.136648

Cited by 98 publications

(82 citation statements)

References 7 publications

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“…Dynamic power corresponds to the power dissipated in charging and recharging internal capacitors in every gate, given by Equation (1).…”

Section: Power and Delay Modelsmentioning

confidence: 99%

“…1 [4] presents a very accurate model for Q crit and its dependency on gates sizes. In the following model, Q crit for the gate i is dependent on gate sizes as below:…”

Section: Single Event Upsetmentioning

confidence: 99%

“…Many approaches have been proposed before [13] [2] [11] [17]. Previous approaches that have taken power considerations into account during transistor sizing include [1] [10] [16]. The approach in [10] utilizes linear dependency between power and gate sizes, however, since it optimizes one path at a time, the approach may lead to suboptimal solutions.…”

Section: Introductionmentioning

confidence: 99%

“…A linear programming approach for exploring the power-delay-area tradeoff for a CMOS circuit is presented in [1]; we use more accurate nonlinear logical effort delay models in this work. Another linear programming based approach is presented in [16].…”

Section: Introductionmentioning

confidence: 99%

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Soft Error-Aware Power Optimization Using Gate Sizing

Dabiri

Nahapetian

Potkonjak

et al.

Lecture Notes in Computer Science

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Abstract. Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft error rates caused by single event upsets (SEU) is becoming exponentially greater. As a consequence of technology feature size reduction, the SEU rate for typical microprocessor logic at the sea level will go from one in hundred years to one every minute. Unfortunately, the gate sizing requirements of power reduction and resiliency against SEU can be contradictory. 1) We consider the effects of gate sizing on SEU and incorporate the relationship between power reduction and SEU resiliency to develop a new method for power optimization under SEU constraints. 2) Although a non-linear programming approach is a more obvious solution, we propose a convex programming formulation that can be solved efficiently. 3) Many of the optimal existing techniques for gate sizing deal with an exponential number of paths in the circuit, we prove that it is sufficient to consider a linear number of constraints. As an important preprocessing step we apply statistical modeling and validation techniques to quantify the impact of fault masking on the SEU rate. We evaluate the effectiveness of our methodology on ISCAS benchmarks and show that error rates can be reduced by a factor of 100% to 200% while, on average, the power saving is simultaneously decreased by less than 7% to 12% respectively, compared to the optimal power saving with no error rate constraints.

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“…Dynamic power corresponds to the power dissipated in charging and recharging internal capacitors in every gate, given by Equation (1).…”

Section: Power and Delay Modelsmentioning

confidence: 99%

“…1 [4] presents a very accurate model for Q crit and its dependency on gates sizes. In the following model, Q crit for the gate i is dependent on gate sizes as below:…”

Section: Single Event Upsetmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Soft Error-Aware Power Optimization Using Gate Sizing

Dabiri

Nahapetian

Potkonjak

et al.

Lecture Notes in Computer Science

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show abstract

“…Many approaches have been proposed [1][2][3][4][5][6][7][8]. Among them, a frequently used mathematical optimization technique for gate sizing is linear programming.…”

Section: Introductionmentioning

confidence: 99%

An iterative gate sizing approach with accurate delay evaluation

Chen¹,

Onodera²,

Tamaru³

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

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Design of Variable Input Delay Gates for Low Dynamic Power Circuits

Raja¹,

Agrawal

Bushnell

2005

Lecture Notes in Computer Science

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The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a v ariable input delay(VID) gate and the maximum difference in delay between any two paths through the same gate is known as "u b ". These gates can be used for minimizing the active power of a digital CMOS circuit using a previosuly described technique called v ariable input delay(VID) logic. This previous publication proposed three different designs for implementating the VID gate. In this paper, we describe a technique for transistor sizing of these three flavors of the VID gate for a given delay requirement. We also describe techniques for calculating the u b of each flavor. We outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance.

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Gate sizing in MOS digital circuits with linear programming

Cited by 98 publications

References 7 publications

Soft Error-Aware Power Optimization Using Gate Sizing

Soft Error-Aware Power Optimization Using Gate Sizing

An iterative gate sizing approach with accurate delay evaluation

Design of Variable Input Delay Gates for Low Dynamic Power Circuits

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