Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress

Abstract

In this work, a metrology was proposed to realize the distribution of fixed oxide trapped charges and grain boundary trapped states. The (continuous-wave green laser crystallization) n-channel thin-film transistors (TFTs) were forced by dc voltage stress, VG=VD. The gate-to-drain capacitance, CGD−VG, with varying frequency of applied small signal was developed. To probe the distribution of these defects, the difference (initial capacitance values minus stressed capacitance values) of CGD−VG with different frequencies was precisely studied.

Degradation Mechanism for Continuous-Wave Green Laser-Crystallized Polycrystalline Silicon n-Channel Thin-Film Transistors under Low Vertical-Field Hot-Carrier Stress with Different Laser Annealing Powers

“…In addition, to understand the creation of trapped charges and states, the overlap capacitance analysis methodology can be effectively employed. [5][6][7][8] The fixed charges in the gate oxide of TFTs are not usually affected by a small applied signal in the C-V measurement. Furthermore, the trap states in the band gap respond to the applied frequency in C-V measurement.…”