Gated low-power clock tree synthesis for 3D-ICs

Lu, Tiantao; Srivastava, Ankur

doi:10.1145/2627369.2627665

Cited by 9 publications

(2 citation statements)

References 14 publications

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“…In [13], the authors minimised 3D clock power using shutdown gates to selectively turn on or off state for necessary or unnecessary clock activities. In 3D IC, shutdown signals require large‐sized TSVs, so they proposed a simulated annealing (SA)‐based algorithm along with a force‐directed TSV placer to decide the selection of shutdown gates and the locations of TSVs under layout white‐space constraint.…”

Section: Literature Surveymentioning

confidence: 99%

An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC

Mondal

Chatterjee²,

Samanta

2018

IET Computers & Digital Techniques

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Effective clock tree design is an important factor for determining chip performance. In this study, the authors present a 3D clock tree design algorithm to enhance the speed and performance of a VLSI chip. The authors propose an algorithm to determine the performance of the clock network by optimising both the clock skew and the dynamic power consumption of the 3D IC clock tree. The authors propose an algorithm for clock tree design based on the Elmore Delay method and routes all the sinks efficiently considering the obstacles with the use of an optimum number of through-silicon-vias (TSVs). The proposed method starts with a segregation technique to divide the sinks into smaller zones. Subsequently, an obstacle avoiding abstract clock tree is constructed with a minimum number of TSVs and buffers. The skew and dynamic power of the tree is calculated. Consequently, the proposed method is compared with recent existing works. The experimental results so obtained are quite encouraging. Nomenclature SinkNode set of sinks die no number of die or stack s n any sink ∈ SinkNode x i , y i coordinates of sink s i Sink NEB , Sink NWB , Sink SEB , Sink SWB set of sinks at direction North East, North West, South East and South West Block, respectively (x lc , y lc) location of centre with x,y position WL wire length Res resistance Cap capacitance

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Section: Literature Surveymentioning

confidence: 99%

An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC

Mondal

Chatterjee²,

Samanta

2018

IET Computers & Digital Techniques

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“…In a 3D clock tree, clock TSVs deliver clock signals from the clock source to each of the clock sinks, while control TSVs provide shutdown signals from a centralized control center to all shutdown gates [Lu and Srivastava 2014]. Since clock synthesis is usually performed after cell placement, layout whitespace for TSVs is limited.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Clock Tree Synthesis for 3D-ICs

Srivastava

2017

ACM Trans. Des. Autom. Electron. Syst.

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We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees' dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. In 3D-ICs, a shutdown gate is connected to a control signal unit through control TSVs, which may cause placement conflicts with existing clock TSVs in the layout due to TSV's large physical dimension. We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering and (2) clock tree embedding with simultaneous shutdown gates' insertion based on simulated annealing (SA) and a force-directed TSV placer. Experimental results indicate that (1) the K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity, and (2) the SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering control TSV's placement. Compared with previous 3D clock tree synthesis techniques, our Kmeans clustering-based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.

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