Gatestacks for scalable high-performance FinFETs

Abstract

formed for contacts. Device width is defined here as Excellent performance (995pA/pm at I0 -94nA/gm and 2Hfin+Wfin. Vdd=IV) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193nm immersion lithography and dry etch. PVD TiN electrodes on HfSiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both dielectric and gate electrode, does not appear to impact scalability or performance. Excellent PMOS performance is achieved for both PEALD and PVD TiN. A new model for threshold voltage VT variability is shown to explain this dependence upon fin width and gate length.Figure 2 Tilted-view SEM image of 16nm fin and 40nm gate after gate etch. The superior gate control of multi-gate devices enables Gate HM is visible on top of gate. continued scaling whilst boosting performance [1-7]. Tall Results FinFETs improve area efficiency and channel doping can be eliminated, thus suppressing band-to-band leakage and A tilted view SEM image (Figure 2) shows a 40nm gate on parametric spread due to dopant fluctuations. The a 16nm fin after gate etch. The gate hard mask is visible on topography of FinFETs does present challenges, especially top ofthe gate for gate formation and etch. We explore the impact of gatestack options upon performance of sub-i15nm wide, 60nm tall, fully-depleted FinFETs. Device fabrication z Si(100) substrates were used as starting material with 145nm buried SiO2 and 60nm SO1. Figure I outlines the process flow. 6Onm SQl on 145nm buried oxide Fin patterning: 193nm i-lithography/ Dry etch 1Onm Gate stack deposition: -lnm interfacial oxide p ALD or MOCVD HfSiO s -PEALD or PVD TiN Gate patterning Extensions: As for NMOS I BF2 for PMOS Spacers: 5nm oxide liner! 3Onm nitride spacer 4onm selective epi-Si growth HDD: As1+0P/for2NMOS/BforPMOS Silicidation: lOnm Ni I RTP1, etch, RTP2 Figure 1 FinFET process applied in this work Fins were defined in the <110> direction. Gate stacks were formed on Inm interfacial oxide with deposition of HfxSil-x0 by ALD or MOCVD, with comparable compositions and thicknesses. This was followed by Figure 3 TEM cross-sections through (left) l3nm fins and (left) 45nm gates plasma-enhanced ALD (PEALD) or PVD of TiN and the of (top) PVD TiN±MOCVD HfSiO stack and (bottom) PEALD TiN ± stack wa cappedwith u-S. Aftergate paterning, ALD HfSiO stack after full device processing.extensions werpedimplated uSpaerAfoermed,epandt4rnmin TMiaegf,isadgts rhw nFiue3 hs

Exploring sub-20nm FinFET design with predictive technology models

“…In order to verify accuracy, the models are fitted with measurement data from industrial publications and parameters such as subthreshold slope, DIBL, etc., are plotted with the PTM-MG trends [13,16,[19][20][21][22][23][24][25][26].…”

CMOS transistor scaling past 32nm and implications on variation

“…A number of intermediate architectures (sometimes called multiple gate FET devices or MuGFETs) have been developed in an attempt to get the best SCE with the minimum process complexity [42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59].…”

“…FinFET: Combines double-gate and vertical device concepts for a more manufacturable version of a double gate device [44][45][46][47][48][49][50][51][52][53][54][55].…”

Identifying the Bottlenecks to the RF Performance of FinFETs

“…Even though FinFETs with impressive Idsat/Ioff values comparable to planar bulk MOSFETs have been reported [2], the reported RF figures of merit of FinFETs are comparatively lower [3]. It has been established that the reason for this is the high parasitics associated with FinFETs on account of their three dimensional nature.…”