Gaussian Pyramid: Comparative Analysis of Hardware Architectures

Abstract

Abstract-The paper addresses a comparison of architectures for hardware implementation of Gaussian image pyramids. Main differences between architectural choices are in the sensor frontend. One side is for architectures consisting of a conventional sensor that delivers digital images and which is followed by digital processors. The other side is for architectures employing a non-conventional sensor with per-pixel embedded pre-processing structures for Gaussian spatial filtering. This later choice belongs to the general category of "artificial retina" sensors which have been for long claimed as potentially advantageous for enhancing throughput and reducing energy consumption of vision systems. These advantages are very important in the internet of things context, where imaging systems are constantly exchanging information. The paper attempts to quantify these potential advantages within a design space in which the degrees of freedom are the number and type of ADCs (single-slope, SAR, cyclic, Σ∆ and pipeline), and the number of digital processors. Results show that speed and energy advantages of pre-processing sensors are not granted by default and are only realized through proper architectural design. The methodology presented for the comparison between focal-plane and digital approaches is a useful tool for imager design, allowing for the assessment of focal-plane processing advantages.

Comparison between Digital Tone-Mapping Operators and a Focal-Plane Pixel-Parallel Circuit

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High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction

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