Ge Devices: A Potential Candidate for Sub-5-nm Nodes?

Sharan, Neha; Eneman, G.; Collaert, N.; Parvais, B.; Spessot, A.; Mocuta, A.; Shaik, Khaja Ahmad; Jang, Doyoung; Schuddinck, P.; Yakimets, D.; Bardon, M. Garcia; Mitard, J.; Arimura, Hiroaki; Bufler, F. M.

doi:10.1109/ted.2019.2944336

Cited by 10 publications

(12 citation statements)

References 14 publications

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“…Therefore, understanding transport properties and electrical characteristics of multigate Ge-based transistors with extremely scaled channel thickness would be very important. 42 In this letter, we demonstrate GAA p-FETs featuring an extremely scaled channel thickness of sub-3 nm, enabled by the formation of a vertical and smooth fin sidewall. This device is the narrowest nanowire FET ever reported.…”

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confidence: 92%

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Ge_0.95Sn_0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width

Kang

Han

et al. 2021

Nano Lett.

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We demonstrate Ge0.95Sn0.05 p-channel gate-all-around field-effect transistors (p-GAAFETs) with sub-3 nm nanowire width (W NW) on a GeSn-on-insulator (GeSnOI) substrate using a top-down fabrication process. Thanks to the excellent gate control by employing an aggressively scaled nanowire structure, Ge0.95Sn0.05 p-GAAFETs exhibit a small subthreshold swing (SS) of 66 mV/decade, a decent on-current/off-current (I ON/I OFF) ratio of ∼1.2 × 106, and a high-field effective hole mobility (μ eff) of ∼115 cm2/(V s). In addition, we also investigate quantum confinement effects in extremely scaled GeSn nanowires, including threshold voltage (V TH) shift and I OFF reduction with continuous scaling of W NW under 10 nm. The phenomena observed from experimental results are substantiated by the calculation of GeSn bandgap and TCAD simulation of electrical characteristics of devices with sub-10 nm W NW. This study suggests Ge-based nanowire p-FETs with extremely scaled dimension hold promise to deliver good performance to enable further scaling for future technology nodes.

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confidence: 92%

“…Furthermore, quantization effects may address the challenge of using Ge-based channel materials where high I OFF is a major concern due to their small bandgaps. Therefore, understanding transport properties and electrical characteristics of multigate Ge-based transistors with extremely scaled channel thickness would be very important …”

mentioning

confidence: 99%

Ge_0.95Sn_0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width

Kang

Han

et al. 2021

Nano Lett.

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“…3(b) [12], and Fig. 3(c) is the starting epitaxial stack used for Ge NSFET which uses a Ge/Si 0.3 Ge 0.7 stack [9], [11]. The proposed starting epitaxial stack studied in this work is shown in Fig.…”

Section: Proposed Nsfet Design Simulation Methodology and Process Flowmentioning

confidence: 99%

“…The Ge/Si 0.3 Ge 0.7 multilayer structure used for Ge NSFET shown in Fig. 3(c) [9], [11] will result in a similar pseudomorphic Ge growth and thickness constraints. Furthermore, the Ge/Si multilayer structure used for Ge NSFET shown in Fig.…”

Section: Proposed Nsfet Design Simulation Methodology and Process Flowmentioning

confidence: 99%

Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

Joshi

Karthikeyan

Hudait

2023

IEEE Trans. Electron Devices

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is possible, and a significant boost in ION (~ 4×) is obtained with 8 layers despite of parasitics induced selfloading. In applications requiring high drive current, increasing the number of stacked Ge nanosheets is the most efficient design pathway to improve circuit delay and area-delay-product. This system shows suitability for low-power and high-performance applications for dimensions down to N0.7, where the ION is ~ 0.6mA/µm and the SS is 81 mV/dec.

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“…In addition, downscaling of silicon (Si) transistors was possible by changing the device geometry from planar to fin field effect transistors (FinFETs). Researchers are now looking into gate-all-around nanosheet FETs (NSFETs) − and high-mobility Ge channel material, to maintain transistor ON current, while reducing supply voltage and footprint. − In the former, crystallographic planes of (100)Si and (110)Si along with HfO 2 -based high-κ gate dielectrics were used for high-performance, low-power Si CMOS logic down to the N3 technology node, , enabling increased integration of complex functionality on a single die. The integration of high-κ gate dielectrics such as HfO 2 and Al 2 O 3 on (100) and (110) crystal planes should not produce defects due to the effect of process temperature during deposition, rather only passivating the surface states and eliminating the interdiffusion of high-κ dielectric and channel materials. , Using these technologically important crystal planes, (100) and (110), from high electron and hole mobility Ge channel materials compared with Si along with a high-κ dielectric, one could make FinFET , or gate-all-around (GAA) NSFET − for high-density and ultralow-power CMOS.…”

Section: Introductionmentioning

confidence: 99%

Carrier Recombination Dynamics of Surface-Passivated Epitaxial (100)Ge, (110)Ge, and (111)Ge Layers by Atomic Layer Deposited Al₂O₃

Hudait

Johnston

Das

et al. 2023

ACS Appl. Electron. Mater.

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Germanium (Ge) and its heterostructures with compound semiconductors offer a unique optoelectronic functionality due to its pseudo-bandgap nature, that can be transformed to a direct bandgap material by providing strain and/or mixing with tin. Moreover, two crystal surfaces, (100)Ge and (110)Ge, that are technologically important for ultralow power fin or nanosheet transistors, could offer unprecedented properties with reduced surface defects after passivating these surfaces by atomic layer deposited (ALD) dielectrics. In this work, the crystallographically oriented epitaxial Ge/AlAs heterostructures were grown and passivated with ALD Al2O3 dielectrics, and the microwave photoconductive decay (μ-PCD) technique was employed to evaluate carrier lifetimes at room temperature. The X-ray photoelectron spectroscopy analysis reveals no role of orientation effect in the quality of the ALD Al2O3 dielectric on oriented Ge layers. The carrier lifetimes measured using the μ-PCD technique were benchmarked against unpassivated Ge/AlAs heterostructures. Excitation wavelengths of 1500 and 1800 nm with an estimated injection level of ∼1013 cm–3 were selected to measure the orientation-specific carrier lifetimes. The carrier lifetime was increased from 390 ns to 565 ns for (100)Ge and from 260 ns to 440 ns for (110)Ge orientations with passivation, whereas the carrier lifetime is almost unchanged for (111)Ge after passivation. This behavior indicates a strong dependence of the measured lifetime on surface orientation and surface passivation. The observed increase (>1.5×) in lifetime with Al2O3-passivated (100)Ge and (110)Ge surfaces is due to the lower surface recombination velocity compared to unpassivated Ge/AlAs heterostructures. The enhancement of carrier lifetime from passivated Ge/AlAs heterostructures with (100)Ge and (110)Ge surface orientations offers a path for the development of nanoscale transistors due to the reduced interface state density.

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Ge Devices: A Potential Candidate for Sub-5-nm Nodes?

Cited by 10 publications

References 14 publications

Ge_0.95Sn_0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width

Ge_0.95Sn_0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width

Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

Carrier Recombination Dynamics of Surface-Passivated Epitaxial (100)Ge, (110)Ge, and (111)Ge Layers by Atomic Layer Deposited Al₂O₃

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Ge Devices: A Potential Candidate for Sub-5-nm Nodes?

Cited by 10 publications

References 14 publications

Ge0.95Sn0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width

Ge0.95Sn0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width

Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

Carrier Recombination Dynamics of Surface-Passivated Epitaxial (100)Ge, (110)Ge, and (111)Ge Layers by Atomic Layer Deposited Al2O3

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Ge_0.95Sn_0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width

Ge_0.95Sn_0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width

Carrier Recombination Dynamics of Surface-Passivated Epitaxial (100)Ge, (110)Ge, and (111)Ge Layers by Atomic Layer Deposited Al₂O₃