General Purpose Computing with Reconfigurable Acceleration

Abstract

In this thesis we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. In order for our solution to be generic, as opposed to related ISA extension approaches, we insert system calls into the original program to control the reconfigurable accelerator using a compiler plug-in. We define specific mechanisms for the communication between the reconfigurable device, the host general purpose processor and the main memory. The reconfigurable device is controlled by the host through system calls provided by the device driver, and initiates communication by raising interrupts; it further has direct accesses to the main memory (DMA) operating in the virtual address space. To do so, the reconfigurable device supports address translation, while the driver serves the device interrupts, ensures that shared data in the host-cache remain coherent, and handles memory protection and paging. The system is implemented using a machine which provides a HyperTransport bus connecting a Xilinx Virtex4-100 FPGA to the host. We evaluate alternative design choices of our proposal using an AES application and accelerating its most computationally intensive function. Our experimental results show that our solution is up to 5× faster than software and achieves a processing throughput equal to the theoretical maximum. n this thesis we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. In order for our solution to be generic, as opposed to related ISA extension approaches, we insert system calls into the original program to control the reconfigurable accelerator using a compiler plug-in. We define specific mechanisms for the communication between the reconfigurable device, the host general purpose processor and the main memory. The reconfigurable device is controlled by the host through system calls provided by the device driver, and initiates communication by raising interrupts; it further has direct accesses to the main memory (DMA) operating in the virtual address space. To do so, the reconfigurable device supports address translation, while the driver serves the device interrupts, ensures that shared data in the host-cache remain coherent, and handles memory protection and paging. The system is implemented using a machine which provides a HyperTransport bus connecting a Xilinx Virtex4-100 FPGA to the host. We evaluate alternative design choices of our proposal using an AES application and accelerating its most computationally intensive function. Our experimental results show that our solution is up to 5× faster than software and achieves a processing throughput equal to the theoretical maximum. Laboratory: Computer Engineering Codenumber : CE-MS

ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces

“…In [13] is shown the implementation of a 512-entries TLB on FPGA in an HyperTransport-based general purpose system. TLB is directly managed by the device driver and ''miss'' cases are handled via interrupt messaging.…”

Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities

“…In [9] is shown the implementation of a 512-entries TLB on FPGA in an HyperTransport-based general purpose system. TLB is directly managed by the device driver and "miss" cases are handled via interrupt messaging.…”

Architectural explorations for streaming accelerators with customized memory layouts

“…Kelm et al [83] used a model based on local input/output buffers on the accelerator with DMA support to access external memory. Brandon et al [84] proposes a platform-independent approach by managing virtual address space inside their accelerator. Several commercially available machines like the SGI Altix-4700 [37] or the Convey HC-1 [85] propose system level models to accelerate application kernels using FPGAs.…”