Generalized algorithms for systematic synthesis of Branch-and-Combine clock networks for meshes, tori, and hypercubes

Recently a novel clock distribution scheme called Branch-and-Combine(BaC) has been proposed. The scheme guarantees constant skew bound irrespective of the size of the clocked network. It utilizes simple nodes to process clock signals such that clock paths are adaptively selected to guarantee constant skew bound. The paper uses a VLSI model to compare the properties of the new scheme to those of the well established H-Tree approach. The H-Tree is a binary tree of simple buffers which is laid out such that leaves are at equal distances from the root. Our study considers clocking 2-D processor meshes of arbitrary sizes. We evaluate and compare the relevant parameters of both schemes in a VLSI layout context. We utilize parameters such as clock skew, link costs, node costs and area efficiency as the basis for comparison. We show that for each BaC network, there is a certain threshold size after which it outperforms the corresponding tree network in terms of skew. We also show that except for node costs, BaC networks outperform the H-Tree, especially when the size of the clocked network is large. As an extension we show that BaC clocking does not suffer from potential pulse disappearance, no matter how large the network is.

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Generalized algorithms for systematic synthesis of Branch-and-Combine clock networks for meshes, tori, and hypercubes

Cited by 2 publications

References 9 publications

On the complexity of designing optimal branch-and-combine clock networks

On the complexity of designing optimal branch-and-combine clock networks

A Comparative Study of SynchronousClocking Schemes for VLSI Based Systems

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