Generalizing timing predictions to set-associative caches

Abstract

Hard real-time systems rely on the assumption that the deadlines of tasks can be met { otherwise the safety of the controlled system is jeopardized. Several scheduling paradigms have b e e n d e v eloped to support the analysis of a task sets and determine if a schedule is feasible. These scheduling paradigms rely on the assumption that the worst-case execution time (WCET) of hard real-time tasks be known a-priori.In the past years, research in the static prediction of WCET has been extended from unoptimized programs on simple CISC processors to optimized programs on pipelined RISC processors, and from uncached architectures to direct-mapped instruction caches. The work presented here goes one step beyond the previous research b y i n troducing the rst framework to handle WCET prediction for set-associative caches. Generalizing the work of static cache simulation of direct-mapped caches to set-associative c a c hes, a formalization of the new method is given and the operational characteristics are presented and discussed by example. Furthermore, WCET predictions for several programs are presented by combining the static cache analysis for set-associative c a c hes with a timing analysis tool. This approach has the advantage that cache con guration details are handled by static cache simulation but remain transparent to the timing analyzer. Overall, this work lls another gap between realistic WCET prediction of contemporary cached architectures and its use in schedulability analysis for hard real-time systems.

Complete worst-case execution time analysis of straight-line hard real-time programs

“…In that approach instructions are classified as always-hit, always-miss, first-miss and first-hit, by analysing the control flow of the program. In [29] the concept is enhanced from direct-mapped to set-associative caches. The Static Cache Simulation only deals with instruction caches, but it is stated in [29], that work is under way to handle data caches as well.…”

“…In [29] the concept is enhanced from direct-mapped to set-associative caches. The Static Cache Simulation only deals with instruction caches, but it is stated in [29], that work is under way to handle data caches as well. Static Cache Simulation can handle nested loops and procedure calls, thus the analysis is more complex than the one used in PTA.…”

A Real-Time Instruction Cache with High Average-Case Performance

“…Healy et al [34], [35] studied static cache simulation for analyzing timing behavior of instruction caches. Mueller [36] examined static cache analysis for set-associative caches. Alt et al [37] studied WCET analysis for caches by using abstract interpretation (AI).…”

Virtual simple architecture (VISA)

“…Most significantly, loop bodies only require a few traversals to bound the WCET for the entire loop. We capture the worst-case behavior of architectural components along execution paths and compose these paths for loops, functions, and, ultimately, the entire application, to derive cycle counts that bound the WCET [1,2,11,23,24,25,26,27,38,39,40]. Figure 1 shows the organization of the timing analysis environment, which has been adapted to model the VISA and the Simplescalar instruction set (PISA) [6].…”