Generation of synthetic sequential benchmark circuits

Hutton, Mike; Rose, Jonathan; Corneil, Derek G.

doi:10.1145/258305.258333

Cited by 25 publications

(53 citation statements)

References 6 publications

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“…These come from three sources, two of which are the MCNC suite [Yanggl], and the RAW benchmark suite [Babb97]. Since we are principally interested in large circuits, we also used the synthetic benchmark circuit generator developed at the University of Toronto [Hutt97] to create several very large benchmarks. Although the latter circuits are actually somewhat more difficult than real circuits, we believe they are perfectly reasonable test cases for the compile time issue.…”

Section: Difficulty Predictionmentioning

confidence: 99%

A fast routability-driven router for FPGAs

Swartz

Betz²,

Rose³

1998

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays - FPGA '98

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Three factors are driving the demand for rapid FPGA compilation. First, as FPGAs have grown in logic capacity, the compile computation has grown more quickly than the compute power of the available computers. Second, there exists a subset of users who are willing to pay for very high speed compile with a decrease in quality of result, and accordingly being required to use a larger FPGA or use more real-estate on a given FPGA than is otherwise necessary. Third, very high speed compile has been a long-standing desire of those using FPGA-based custom computing machines, as they want compile times at least closer to those of regular computers. This paper focuses on the routing phase of the compile process, and in particular on routability-driven routing (as opposed to timing-driven routing). We present a routing algorithm and routing tool that has three unique capabilities relating to very high-speed compile: For a "low stress" routing problem (which we define as the case where the track supply is at least 10% greater than the minimum number of tracks per channel actually needed to route a circuit) the routing time is very fast. For example, the routing phase (after the netlist is parsed and the routing graph is constructed) for a 20,000 LUT/FF pair circuit with 30% extra tracks is only 23 seconds on a 300 MHz Sparcstation.For low-stress routing problems the routing time is nearlinear in the size of the circuit, and the linearity constant is very small: 1.1 ms per LUT/FF pair, or roughly 55,000 LUT/FF pairs per minute.For more difficult routing problems (where the track supply is close to the minimum needed) we provide a method that quickly identifies and subdivides this class into two sub-classes: (i) those circuits which are difficult (but possible) to route and will take significantly more time than low-stress problems, and (ii) those circuits which are impossible to route. In the first case the user can choose to continue or reduce the amount of logic; in the second case the user is forced to reduce the amount of logic or obtain a larger FPGA.

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Section: Difficulty Predictionmentioning

confidence: 99%

A fast routability-driven router for FPGAs

Swartz

Betz²,

Rose³

1998

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays - FPGA '98

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“…These benchmarks are from the MCNC suite [26], the RAW benchmark suite [4], and a benchmark circuit generator [18]. All experiments were run on a 366MHz Celeron-based PC with 256MB of memory.…”

Section: Resultsmentioning

confidence: 99%

Tolerating operational faults in cluster-based FPGAs

Lakamraju

Tessier

2000

Proceedings of the 2000 ACM/SIGDA Eighth International Symposium on Field Programmable Gate Arrays

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in recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain hardware redundancy to allow for continued operation in the presence of operational faults, the need to recover faulty hardware and return it to full functionality quickly and efficiently is great. In addition to providing functional density, FPGAs provide a level of fault tolerance generally not found in mask-programmable devices by including the capability to reconfigure around operational faults in the field. In this paper, incremental CAD techniques are described that allow functional recovery of FPGA design configurations in the presence of single or multiple operational faults. Our preferred approach to fault recovery takes advantage of device routing hierarchy in architectural families such as Xilinx Virtex [2] and Alters Apex [3] to quickly swap unused logic and routing resources in place of faulty ones within logic clusters. These algorithms allow for straightforward implementation within a local fault-tolerant system without the need to access a remote processing location. If initial recovery attempts through localized swapping fail, an incremental router based on the widely-used PathFinder maze routing algorithm [10] can be applied remotely in an attempt to form connections between newly-allocated logic and interconnect based on the history of the initial design route.

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“…For this reason, the first successful trials of benchmark generation were based on applying a sequence of random transformations on an initial (existing) circuit [4, 51. Hutton et al [6] addressed the problem of random generation of circuits "from scratch". They defined properties such as size, delay, physical shape, edge-length distribution, and fanout distribution to describe the physical characteristics and generated circuits with an exact parameterization ("clones" of existing circuits).…”

Section: Introductionmentioning

confidence: 99%

Towards synthetic benchmark circuits for evaluating timing-driven CAD tools

Stroobandt

Verplaetse

Campenhout

1999

Proceedings of the 1999 International Symposium on Physical Design

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ABSTRKTFor the development and evaluation of CAD-tools for partitioning, floorplauning, placement, and routing of digital circuits, a huge amotmt of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits for use in evaluation tools, one could consider to actually generate such circuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timing-driven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. However, the synthetic benchmark circuits are still very redundant, compared to existing sets of real benchmarks. It is shown that a correlation exists between the degree of redundancy and key circuit parameters.

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Generation of synthetic sequential benchmark circuits

Cited by 25 publications

References 6 publications

A fast routability-driven router for FPGAs

A fast routability-driven router for FPGAs

Tolerating operational faults in cluster-based FPGAs

Towards synthetic benchmark circuits for evaluating timing-driven CAD tools

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