Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verification

This paper presents a methodology to automatically generate SystemC protocol implementation, starting from its specification given through UML sequence diagrams. The methodology merges such diagrams into a single one, which is then used to generate the SystemC code. Two algorithms are proposed for the merging and refinement step, respectively. SCNSL network simulator is exploited to simulate the generated code in a complete network scenario. As case study, the methodology is applied to sequence diagrams contained into IEEE 802.15.4 protocol standard specification.

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“…Ebeid at el. [8,7] presented a methodology to automatically translates sequence diagrams with checkers into HDL code for model verification.…”

Section: State Of the Artmentioning

confidence: 99%

Automatic Network Protocol Synthesis from UML Sequence Diagrams

Ebeid

Fummi

Quaglia

et al. 2013

2013 14th International Workshop on Microprocessor Test and Verification

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“…This constitutes a significant drawback since e. g. methods such as [8], [9], [10], [11], [12], [13] which are aiming for proving the correctness of corresponding models do not support CCSL constraints. Vice versa, CCSL checkers as introduced in [3], [4], [5], [6] do not consider the functional behavior.…”

Section: Introductionmentioning

confidence: 99%

A generic representation of CCSL time constraints for UML/MARTE models

Peters

Wille

Przigoda

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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The complexity of today's embedded and cyberphysical systems is rapidly increasing and makes the consideration of higher levels of abstraction during the design process inevitable. In this context, the impact of modeling languages such as UML and its profiles such as MARTE is growing. Here, CCSL provides a formal description of timing constraints which have to be enforced on the considered system. This builds the basis for many further design steps and can be used e. g. for checking the consistency of the specification, for code generation, or for proving whether the time constraints have correctly been implemented at lower abstraction levels. However, most of the approaches available thus far usually focus on sole design tasks only -often even without an explicit consideration of the system's functional behavior. In this work, we are aiming for overcoming this drawback by providing a method to automatically generate a generic representation of a set of clock constraints in terms of a transition relation. Afterwards, the resulting transition relation can easily be utilized for the above mentioned design tasks. A discussion on the applicability of the generic description as well as an exemplary evaluation shows the promise of the proposed generic representation.

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“…The considered scenario is the following: Given an initial MARTE specification, all structural and functional aspects of the system have already been implemented in SystemC (e. g. using the approaches from [6], [7], [8]), i. e. a SystemC implementation composed of several modules, attributes, methods, but also clocks is already available (see Fig. 3).…”

Section: B Systemcmentioning

confidence: 99%

“…Since the clock minutes is chronometric, the period to the internal clock is accordingly adjusted (line 14). Furthermore, a port is added for every clock which is directed by the TimeController (see lines [5][6][7][8][9][10]. This is needed in order to trigger the respective tickings.…”

Section: B Generating Systemcmentioning

confidence: 99%

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Generating SystemC Implementations for Clock Constraints Specified in UML/MARTE CCSL

Peters

Wille

Drechsler

2014

2014 19th International Conference on Engineering of Complex Computer Systems

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Abstract-Due to the increasing complexity of today's embedded systems, the design on higher levels of abstraction becomes more and more important. In this context, modeling languages such as UML and its profile MARTE received significant attention in the recent past. They provide formal descriptions that can be exploited to automatically generate initial implementations of a system e. g. in SystemC. While corresponding approaches have been developed in the past, they often focused on functional specifications. Besides that, also non-functional behavior such as clocking constraints needs to be considered in this process. In this work, we propose an approach which addresses this gap. Given a formal specification of clocking constraints specified in the Clock Constraint Specification Language (CCSL; a MARTE accessory), we propose an automatic code generation scheme which enriches an existing SystemC implementation by a module triggering the desired clocks in the system.

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Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verification

Cited by 14 publications

References 4 publications

Automatic Network Protocol Synthesis from UML Sequence Diagrams

Automatic Network Protocol Synthesis from UML Sequence Diagrams

A generic representation of CCSL time constraints for UML/MARTE models

Generating SystemC Implementations for Clock Constraints Specified in UML/MARTE CCSL

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