Generic Connectivity-Based CGRA Mapping via Integer Linear Programming

Abstract

Coarse-grained reconfigurable architectures (CGRAs) are programmable logic devices with large coarsegrained ALU-like logic blocks, and multi-bit datapath-style routing. CGRAs often have relatively restricted data routing networks, so they attract CAD mapping tools that use exact methods, such as Integer Linear Programming (ILP). However, tools that target general architectures must use large constraint systems to fully describe an architecture's flexibility, resulting in lengthy run-times. In this paper, we propose to derive connectivity information from an otherwise generic device model, and use this to create simpler ILPs, which we combine in an iterative schedule and retain most of the exactness of a fully-generic ILP approach. This new approach has a speed-up geometric mean of 5.88× when considering benchmarks that do not hit a time-limit of 7.5 hours on the fully-generic ILP, and 37.6× otherwise. This was measured using the set of benchmarks used to originally evaluate the fully-generic approach and several more benchmarks representing computation tasks, over three different CGRA architectures. All run-times of the new approach are less than 20 minutes, with 90th percentile time of 410 seconds. The proposed mapping techniques are integrated into, and evaluated using the open-source CGRA-ME architecture modelling and exploration framework [1].

RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays

“…In subsection III-E, we compare the execution time of the proposed hardware P&R to a software implementation on a high-performance multicore CPU. Finally, in subsection III-F, we compare the P&R quality and execution time to VPR [11], CGRA-ME [27], and the approach proposed in [21].…”

“…Table VI presents the mapping costs and execution times for mesh-plus architecture in comparison to previous work: 1) VPR [11] uses the well-known simulated annealing FPGA P&R; 2) CGRA-ME [27] uses integer linear programming (ILP) and does not scale to larger graphs. Our P&R approach achieves the same wire length results compared to VPR and is 37× faster.…”

“…We evaluate three overlay architectures and the trade-offs among mapping time and performance. We compare our P&R to VPR [11], CGRA-ME [27], and a time-multiplexer approach [20], [21]. RESHAPE outperforms previous works in the P&R execution time and CGRA performance.…”

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

“…Hy-CUBE [60]), or CGRA designs frameworks/generators (e.g. CGRA-ME [61], [62]). Furthermore, ADRES has been taped out on silicon, for example in the Samsung Reconfigurable Processor (SRP) and the follow-up UL-SRP [63] architecture.…”

Algoritmos de Posicionamento e Roteamento baseados em Travessia de Grafo para Arquiteturas Reconfiguráveis de Grão Grosso (CGRA)

“…Este trabalho propõe algoritmos para o problema de posicionamento e roteamento (P&R), que é NP-Completo. Vários trabalhos apresentaram soluc ¸ões exatas e heurísticas como, por exemplo, Simulated Annealing [Murray and et al 2020], heurísticas de travessia [Ferreira and et al 2007], particionamento e técnicas de programac ¸ão linear [Walker and et al 2019]. Contudo, o tempo de execuc ¸ão, a qualidade da soluc ¸ão e a limitac ¸ão para o tamanho máximo do grafo de entrada ainda são barreiras para a soluc ¸ão do problema.…”