Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA

Mičulka, Lukáš; Kotásek, Zdenĕk

doi:10.1109/ddecs.2014.6868784

Cited by 9 publications

(4 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…User logic must trigger and monitor the This particular polynomial provides detection of all burst errors up to 32 bits in a data block and detection of all 5 random errors for data blocks smaller than 31 Kib [16]. When operating in D 2 PR-CRC mode, the theoretical throughput can be maximized by finding the data block size value that maximize Equation 3. In the considered test case, the data block size has been set to BlkS = 5.5Kib to maximize the reconfiguration throughput.…”

Section: Resultsmentioning

confidence: 99%

“…Modern SRAM-based FPGAs offer Dynamic Partial Reconfiguration (DPR) features [2], i.e., the ability to run-time change the functionality implemented by selected portions of a circuit while maintaining the rest of the design in a fully operating state. Although DPR can be used to increase reliability figures of a system [3], its adoption in applications demanding high reliability is actually very limited for two main reasons. The first one concerns the additional complexity introduced during the system design phase.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs

Carlo

Prinetto

Trotta

et al. 2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

Thanks to their flexibility, increasing performances and low Non-Recurrent Engineering costs, SRAM-based Field Programmable Gate Array (FPGA) devices often represent the preferred platforms for the final deployment of highly reliable systems. In this context, Dynamic Partial Reconfiguration (DPR) is far from being widely adopted due to the additional complexity introduced during the hardware design phase, and the dependability issues related to the FPGA reconfiguration process itself. This paper presents a portable open-source controller for safely enabling self dynamic and partial reconfiguration of systems implemented on Xilinx FPGAs. The controller embeds configurable error detection and correction circuitry that enables a safe DPR by monitoring for partial bitstreams data errors. Experiments highlight the high performances achieved and the limited hardware resources needed to implement it on different devices. The HDL source code has been made available through the popular open-source Cobham Gaisler GRLIB IP-cores library. 1

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs

Carlo

Prinetto

Trotta

et al. 2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

show abstract

“…Herein, partial reconfiguration is the major approach to repair components and mitigate permanent faults. The research of [108] proposes a small flexible controller to drive the reconfiguration process in PSF presence. This technique uses alternative pre-synthesized configurations for permanent fault reduction, bitstream relocation reducing the required bitstream, and fault type detection in case of success in previous repairs, etc.…”

Section: E Circuit-level Resiliencementioning

confidence: 99%

Dependable DNN Accelerator for Safety-Critical Systems: A Review on the Aging Perspective

Moghaddasi,

Gorgin,

Lee

2023

IEEE Access

View full text Add to dashboard Cite

Nowadays, artificial intelligence (AI) and deep learning (DL) progressively adapt to various spheres of our lives. These disciplines contain safety-critical applications such as autonomous driving with a high risk of human injury in the case of malfunction, requiring a high promise of dependability. Even the dependability becomes more crucial as shrinking CMOS technology feature size worsens the resilience concerns due to factors like aging. This paper addresses the overarching dependability issue of advanced deep neural networks (DNN) accelerators from the aging perspective. Especially, a comprehensive survey and taxonomy of techniques used to evaluate and mitigate aging effects are introduced. We cover different aging effects like permanent faults, timing errors, and lifetime issues. We review research by the layer-wise approach and categorize several resilience classes to bring out major features. The concluding part of this review highlights the questions answered and several future research directions. This study is expected to benefit researchers in different areas of DNN deployment, especially the dependability of this emergent paradigm.

show abstract

“…First, we developed methodology for design of FTSs based on duplex and TMR architectures and their combination with online-checkers which were used to increase their fault detection capabilities [5]. Then, to enable active fault tolerance we developed Generic Partial Dynamic Reconfiguration Controller (GPDRC) [6] [7] as the main recovery mechanism in situations when an SEU attacks the FTS implementation. The GPDRC is a universal component which can be included in almost any FTS for providing self repairing ability through the reconfiguration process of Partial Reconfiguration Modules (PRMs) in configuration memory of Xilinx SRAM-based FPGAs.…”

Section: Previous Work and Goals Of The Researchmentioning

confidence: 99%

Towards a state synchronization methodology for recovery process after partial reconfiguration of fault tolerant systems

Szurman¹,

Mičulka

Kotásek

2014

2014 9th International Conference on Computer Engineering &Amp; Systems (ICCES)

Self Cite

View full text Add to dashboard Cite

Modern fault tolerant systems implemented into FPGAs integrate very often hardware redundancy together with fault tolerant approaches based on active fault recovery and the system reconfiguration. Space and safety-critical applications are examples of systems where the principles of fault tolerance and recovery techniques have increasing importance. Except of fault-masking behavior and FPGA partial reconfiguration, also the synchronization of reconfigured circuit copy with remaining circuits which are during the recovery process still operating,is an integral part of the recovery process in these systems.The synchronization process is closely related to the system architecture, specific requirements and functionality. Our aim is to propose specific methodology to design and implement the most suitable synchronization procedure for the recovery of target fault tolerant system. In this paper, basic principles of our synchronization methodology are described together with generic architecture for synchronization in fault tolerant systems, which was designed for reconfigurable fault tolerant CAN bus control system. This system and performed experiments are in the paper described as well.

show abstract

Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA

Cited by 9 publications

References 7 publications

A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs

A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs

Dependable DNN Accelerator for Safety-Critical Systems: A Review on the Aging Perspective

Towards a state synchronization methodology for recovery process after partial reconfiguration of fault tolerant systems

Contact Info

Product

Resources

About