Genetic Algorithm applied to the Functional Verification in Digital Systems

Abstract

A critical stage of a hardware design is the hardware verification phase. The verification phase corresponds to the biggest bottleneck in a hardware design. The VeriSC methodology is a methodology to perform the hardware verification through of functional verification. In this work, we propose a novel improvement in VeriSC methodology data generation using Genetic Algorithms and feedback approach. The proposed algorithm will modify the data generation of this methodology, whose objective is to reduce the verification time and to improve the generated data. A DPCM and two modules of MPEG-DECODER are used as case studies. The results not only show that the proposed approach can achieve functional coverage with good performance, but also show that the execution time is better or similar to the former method used in VeriSC methodology. These results demonstrate the Genetic Algorithm approach explores the search space better than older approach. The data generation performed can also be used in other methodologies without any problem.

Coverage Fulfillment Automation in Hardware Functional Verification Using Genetic Algorithms

“…Despite this difference, the approaches currently developed reached the maximum coverage score several times. This paper [19] can be considered a continuation of the work in [18]. One of the targets of the mentioned work was to reach the same functional coverage items many times.…”

“…Following their, in the current work various approaches based on genetic algorithms were created and fine-tuned. An important difference between [19] and the current work is that in [19] each individual consisted of values needed by multiple inputs of the DUT. In all three examples analyzed in the current work, the individuals are used to build sequences of values to be driven at the same input of the DUT.…”