Germanium out diffusion in SiGe-based HfO2 gate stacks

Martínez, E.; Nolot, Emmanuel; Barnes, Jean‐Paul; Mazel, Yann; Bernier, Nicolas; Muthinti, Raja; Jagannathan, H.; Lee, Choonghyun; Gambacorti, N.

doi:10.1116/1.5027072

Cited by 3 publications

(4 citation statements)

References 15 publications

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“…For I2, the depth profile shows a diffusion of Ge ox within the HfO 2 layer. Such a behavior was already reported for HfO 2 / Ge or SiGe by several groups [32][33][34] and could be responsible for the dielectric permittivity, leakage current, and interface state density issues. 35 In the case of GeSn, Ge diffusion into the HfO 2 layer results in a modification of the Ge 1Àx Sn x stoichiometry close to the interface and, thus, a Sn segregation.…”

supporting

confidence: 61%

Improvement of the electrical performance of Au/Ti/HfO2/Ge0.9Sn0.1 p-MOS capacitors by using interfacial layers

Haffner

Mahjoub

Labau

et al. 2019

Applied Physics Letters

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The impact of different interfacial layers (ILs) on the electrical performances of Au/Ti/HfO 2 /Ge 0.9 Sn 0.1 metal oxide semiconductor (MOS) capacitors is studied. Parallel angle resolved x-ray photoelectron spectroscopy measurements show that germanium diffuses into the HfO 2 layer when no IL is used. This results in an increase in the tin content at the interface and a high interface state density. We demonstrate that the use of an IL prevents germanium and HfO 2 intermixing and improves the electrical performance of MOS capacitors. Several ILs are studied such as alumina (Al 2 O 3 ) and plasma oxidized GeSn (GeSnO x ) prior to HfO 2 deposition. C-V measurements correlated with simulations made by a customized analytical model indicate an interface state density of 5 Â 10 11 eV À1 cm À2 for the HfO 2 /GeSnO x /Ge 0.9 Sn 0.1 gate stack. This result is promising for the integration of high mobility GeSn channels in CMOS devices.

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supporting

confidence: 61%

Improvement of the electrical performance of Au/Ti/HfO2/Ge0.9Sn0.1 p-MOS capacitors by using interfacial layers

Haffner

Mahjoub

Labau

et al. 2019

Applied Physics Letters

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“…Specifically, the growth of high-k dielectrics on alternate channel materials such as Ge, InAs, and InSb without Fermi level pinning and high interface defect levels is non-trivial. [165][166][167][168][169][170][171] Likewise, the nucleation and growth of high-k dielectrics on potential 2D channel materials and insulators such as graphene and MoS 2 is also non-trivial. [172][173][174][175] Similarly, the insertion of air-gaps in metal interconnects while removing the low-k ILD from consideration at the targeted metal level, creates new complexities for the following low-k ILD used to pinchoff the air-gap structure shown in Figure 5.…”

Section: What Is Left For High-k and Low-k Dielectrics?mentioning

confidence: 99%

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

Jenkins

Austin

Conley

et al. 2019

ECS J. Solid State Sci. Technol.

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High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges. We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling. We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful” requirements for the various enabling dielectric hardmask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements. We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.

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“…The stoichiometry of the PCM and the chemical depth-profile of the PCM stack must be moni- method. 8,9 PP-TOFMS is now a technique mature enough to characterize industry-relevant samples [10][11][12] in research and development and industrial environments.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, low matrix effects and uniform sensitivity allow direct, standard‐free, semiquantitative analyses based on the ion beam ratio (IBR) method 8,9 . PP‐TOFMS is now a technique mature enough to characterize industry‐relevant samples 10–12 in research and development and industrial environments.…”

Section: Introductionmentioning

confidence: 99%

Accelerating the development of phase‐change random access memory with in‐fab plasma profiling time‐of‐flight mass spectrometry

Nolot

Mazel

Barnes

et al. 2020

Surface & Interface Analysis

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We demonstrate the potential of using plasma profiling time-of-flight mass spectrometry (PP-TOFMS) to accelerate process developments for phase-change random access memory (PCRAM) applications, which require advanced materials with composition-driven properties. We assess the performances of PP-TOFMS for the chemical depth-profiling of GeSbTe phase change materials, first after deposition steps to investigate the top surface layer and the incorporation of silicon into the amorphous matrix, then after the thermal annealing step to refine in situ capping strategies, and finally in close loop with etching process steps. Comparison of reference-free semiquantitative PP-TOFMS analysis based on ion beam ratio with Rutherford backscattering spectrometry shows remarkable agreement (10% relative). PP-TOFMS proves to be a fast screening tool, which allows process monitoring and selection of samples that indeed need more complex analysis. K E Y W O R D S chemical depth profile, metrology, phase change memory, plasma profiling time-of-flight mass spectrometry

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Germanium out diffusion in SiGe-based HfO2 gate stacks

Cited by 3 publications

References 15 publications

Improvement of the electrical performance of Au/Ti/HfO2/Ge0.9Sn0.1 p-MOS capacitors by using interfacial layers

Improvement of the electrical performance of Au/Ti/HfO2/Ge0.9Sn0.1 p-MOS capacitors by using interfacial layers

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

Accelerating the development of phase‐change random access memory with in‐fab plasma profiling time‐of‐flight mass spectrometry

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