Gettering in silicon-on-insulator wafers with polysilicon layer

Savin, Hele; Yli-Koski, Marko; Haarahiltunen, Antti; Virkkala, Ville; Talvitie, Heli; Asghar, Muhammad Imran; Sinkkonen, J.; Hintsala, Jouko

doi:10.1016/j.mseb.2008.12.024

Cited by 6 publications

(4 citation statements)

References 18 publications

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“…[ 17 ] Moreover, it was reported that after high‐temperature annealing, the gettering efficiencies of backside polycrystalline silicon layers are greatly reduced. [ 16 ] Unfortunately, these treatments are commonly present in power device processing and our result greatly reconsiders the importance of a polycrystalline silicon layer for gettering of iron contamination.…”

Section: Resultsmentioning

confidence: 98%

“…This result can be surprising, taking into account recent literature on gettering effect of grain boundaries in multicrystalline silicon [12,15] and in polycrystalline silicon layers. [7,16] However, it should be noted that several characteristics of the deposited polycrystalline silicon layer, such as deposition temperature and thermal history, grain size, and doping can greatly influence the impurity gettering efficiency. Iron gettering in polysilicon was found to occur significantly after slow cooling below 900 C or by isothermal annealing at 700 C. [17] Moreover, it was reported that after high-temperature annealing, the gettering efficiencies of backside polycrystalline silicon layers are greatly reduced.…”

Section: Resultsmentioning

confidence: 99%

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Internal and External Gettering of Iron Contamination in Power Technologies

Frascaroli

Roffarello

Mica

2021

Physica Status Solidi (a)

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Substrate gettering and the contribution to the contamination reduction of backside layers are evaluated after high‐temperature annealing, following intentional iron contamination at the backside in silicon epitaxial wafers typical of power technologies. Iron is detected at the frontside by deep‐level transient spectroscopy within a depth corresponding to the actual devices. Herein, contamination occurring at the beginning of the semiconductor process flow is simulated and the role of the different gettering mechanisms is isolated. Substrate boron in epitaxial p over p+ wafers is effective in more than halving iron contamination at the front compared with a p‐only substrate, especially at high contamination doses. In the absence of a specific thermal cycle for oxygen precipitation and growth in the bulk, long thermal treatment at 1200 °C induces a significant precipitate growth even in the beginning of the process, greatly contributing to iron gettering in the bulk. However, this effect is found to strongly depend on the silicon condition after crystal growth. No significant contribution to iron gettering from a backside polycrystalline silicon layer is found after high‐temperature annealing, whereas a backoxide acts as diffusion barrier, effectively screening the substrate from contamination only for short thermal treatments or annealing temperature below 1000 °C.

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Section: Resultsmentioning

confidence: 98%

Section: Resultsmentioning

confidence: 99%

Internal and External Gettering of Iron Contamination in Power Technologies

Frascaroli

Roffarello

Mica

2021

Physica Status Solidi (a)

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“…For example, it is possible to include the iron segregation gettering effect into simulations when the macroscopic segregation coefficient of iron between monocrystalline and polycrystalline silicon is known as a function of temperature. The earlier results of the G‐SOI structure did not make it possible to determine the segregation and precipitation parameters for the polysilicon interlayer 3, 4, because the device layer was too thin for the steady‐state iron concentration determination.…”

Section: Introductionmentioning

confidence: 99%

Iron segregation in silicon‐on‐insulator wafer with polysilicon interlayer

Yli-Koski

Haarahiltunen

Hintsala

et al. 2012

Physica Status Solidi (a)

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We have studied iron gettering from monocrystalline silicon device layer into polycrystalline silicon (polysilicon) interlayer in thick bonded silicon‐on‐insulator (SOI) wafers. The results show that the polysilicon interlayer acts as an efficient gettering layer for iron. The gettering takes place via both the segregation and precipitation although the dominant gettering mechanism is segregation at low contamination levels. The activation energy of the segregation coefficient between the monocrystalline silicon and the polysilicon interlayer was found to be Ea = 1.9 ± 0.2 eV.

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“…Apart from acting as a planarization layer for the wafer bonding, the poly-Si layer may act as a gettering layer. 8 To show that the substrate is suitable for processing in a foundry, this paper presents fabrication of 150-mm substrates. Since single-crystalline SiC is expensive and not even available in 150-mm wafer size, here we used poly-SiC wafers.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Characterization of 150-mm Silicon-on-Polycrystalline Silicon Carbide Substrates

Lotfi

Vallin

et al. 2011

Journal of Elec Materi

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Silicon-on-insulator (SOI) substrates can reduce radiofrequency (RF) substrate losses due to their buried oxide (BOX). On the other hand, the BOX causes problems since it acts as a thermal barrier. Oxide has low thermal conductivity and traps heat generated by devices on the SOI. This paper presents a hybrid substrate which uses a thin layer of polycrystalline silicon and polycrystalline silicon carbide (Si-on-poly-SiC) to replace the thermally unfavorable BOX and the silicon substrate. Substrates of 150 mm were fabricated by wafer bonding and shown to be stress and strain free. Various electronic devices and test structures were processed on the hybrid substrate as well as on a low-resistivity SOI reference wafer. The substrates were characterized electrically and thermally and compared with each other. Results showed that the Si-on-poly-SiC wafer had 2.5 times lower thermal resistance and exhibited equal or better electrical performance compared with the SOI reference wafer.

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Gettering in silicon-on-insulator wafers with polysilicon layer

Cited by 6 publications

References 18 publications

Internal and External Gettering of Iron Contamination in Power Technologies

Internal and External Gettering of Iron Contamination in Power Technologies

Iron segregation in silicon‐on‐insulator wafer with polysilicon interlayer

Fabrication and Characterization of 150-mm Silicon-on-Polycrystalline Silicon Carbide Substrates

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