GF(2⁴) multiplier in hardware using discrete neural network

Abstract

This article describes a new structure of finite fields multiplier based on Mastrovito multiplier. This architecture has linear threshold gates as the processing units, which is the basic element of a discrete neural network. One of the great advantages of using neural networks implemented with discrete linear threshold gates is that it reduces the complexity of certain circuits before implemented with traditional logic (AND, OR, and NOT), thus making more complex circuits can be designed in a more simplified form by reducing the number of necessary ports. The entire circuit was designed and simulated using CADENCE tools with technology IBM018.