Global Elimination Algorithm and Architecture Design for Fast Block Matching Motion Estimation

Huang, Yu-Wen; Chien, Shao-Yi; Hsieh, Bing-Yu; Chen, Liang-Gee

doi:10.1109/tcsvt.2004.828321

Cited by 67 publications

(43 citation statements)

References 21 publications

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“…Finally, we compute the SAD at the M search positions to find the final motion vector (MV). In [103], we found that L = 2 and M = 7 are suitable parameters for CIF and QCIF under N = 16 and p = 16 or p = 32.…”

Section: Global Elimination Algorithmmentioning

confidence: 90%

“…5, instead of feeding the maximum SSAD value back to compare for replacement, we give each SSAD value an unique 2-bit tag and feed the tag with the maximum SSAD back for comparison. The gate count of the comparator tree is reduced from 1.5 to 1.1 K, compared with the previous version [103] for M = 3. Figure 6(a) illustrates a GEA-PE.…”

Section: Proposed Parallel Geamentioning

confidence: 97%

“…In [103], we proposed a global elimination algorithm (GEA) to remove the branches of SEA/MSEA. The data flow becomes more regular for hardware.…”

Section: Proposed New Designmentioning

confidence: 99%

“…The systolic module utilizes vertical data reuse, and thus the subblock sums at the search positions (m, −p + 1) (m, p − 1) can be obtained in the following (2p − 1) cycles. Compared with the original systolic module in [103], the improved systolic module not only removes the redundant computation of subblock sums but also reduces the resolution of subblock sums from 12-bit to eight-bit. The gate count of this part is reduced from 6.0 to 4.7 K.…”

Section: Proposed Parallel Geamentioning

confidence: 99%

“…The MAX unit outputs the larger value of its two inputs, and the EQU unit tells if the two given inputs are the same. The previous architecture shown in [103] finds the maximum SSAD value and feed it back to compare with three stored values to see if a stored value should be replaced. Then, a CHECK unit is to ensure that only one stored value will be replaced if more than one stored values are equal to the maximum.…”

Section: Proposed Parallel Geamentioning

confidence: 99%

See 4 more Smart Citations

Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results

Huang

Chen

Tsai

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

139

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Abstract. Block matching motion estimation is the heart of video coding systems. During the last two decades, hundreds of fast algorithms and VLSI architectures have been proposed. In this paper, we try to provide an extensive exploration of motion estimation with our new developments. The main concepts of fast algorithms can be classified into six categories: reduction in search positions, simplification of matching criterion, bitwidth reduction, predictive search, hierarchical search, and fast full search. Comparisons of various algorithms in terms of video quality and computational complexity are given as useful guidelines for software applications. As for hardware implementations, full search architectures derived from systolic mapping are first introduced. The systolic arrays can be divided into inter-type and intra-type with 1-D, 2-D, and tree structures. Hexagonal plots are presented for system designers to clearly evaluate the architectures in six aspects including gate count, required frequency, hardware utilization, memory bandwidth, memory bitwidth, and latency. Next, architectures supporting fast algorithms are also reviewed. Finally, we propose our algorithmic and architectural co-development. The main idea is quick checking of the entire search range with simplified matching criterion to globally eliminate impossible candidates, followed by finer selection among potential best matched candidates. The operations of the two stages are mapped to the same hardware for resource sharing. Simulation results show that our design is ten times more area-speed efficient than full search architectures while the video quality is competitively the same.

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Section: Global Elimination Algorithmmentioning

confidence: 90%

Section: Proposed Parallel Geamentioning

confidence: 97%

“…In [103], we proposed a global elimination algorithm (GEA) to remove the branches of SEA/MSEA. The data flow becomes more regular for hardware.…”

Section: Proposed New Designmentioning

confidence: 99%

Section: Proposed Parallel Geamentioning

confidence: 99%

Section: Proposed Parallel Geamentioning

confidence: 99%