Global Interconnect Optimization

Daboul, Siad; Held, Stephan; Natura, Bento; Rotter, Daniel

doi:10.1109/iccad45719.2019.8942155

Cited by 3 publications

(2 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Cost-distance Steiner trees are heavily used in VLSI routing and interconnect optimization [10,5] to achieve a low power consumption and, simultaneously, a fast chip speed.…”

Section: Given Amentioning

confidence: 99%

Further Improvements on Approximating the Uniform Cost-Distance Steiner Tree Problem

Held¹,

Spitzley²

2022

Preprint

View full text Add to dashboard Cite

In this paper, we consider the Uniform Cost-Distance Steiner Tree Problem in metric spaces, a generalization of the well-known Steiner tree problem. Cost-distance Steiner trees minimize the sum of the total length and the weighted path lengths from a dedicated root to the other terminals, which have a weight to penalize the path length. They are applied when the tree is intended for signal transmission, e.g. in chip design or telecommunication networks, and the signal speed through the tree has to be considered besides the total length.Constant factor approximation algorithms for the uniform cost-distance Steiner tree problem have been known since the first mentioning of the problem by Meyerson, Munagala, and Plotkin [14]. Recently, the approximation factor was improved from 2.87 to 2.39 by Khazraei and Held [12]. We refine their approach further and reduce the approximation factor down to 2.15.

show abstract

“…Cost-distance Steiner trees are heavily used in VLSI routing and interconnect optimization [10,5] to achieve a low power consumption and, simultaneously, a fast chip speed.…”

Section: Given Amentioning

confidence: 99%

Further Improvements on Approximating the Uniform Cost-Distance Steiner Tree Problem

Held¹,

Spitzley²

2022

Preprint

View full text Add to dashboard Cite

show abstract

“…Since interconnect latency has become a dominant factor in determining system performance, it is no longer sufficient to consider only congestion. Daboul et al [143] balanced a multitude of different objectives via the resource sharing framework,such as timing, power and wirelength. In the routing process, the addition of timing constraints and power constraints is more in line with actual industrial manufacturing and is of great significance in both theoretical research and actual production.…”

Section: Performance-driven Routingmentioning

confidence: 99%

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

et al. 2020

View full text Add to dashboard Cite

Global Routing (GR) is a crucial and complex stage in the Very Large-Scale Integration (VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall chip performance. Steiner tree construction is one of the basic models of VLSI physical design, which is usually used in the initial topology creation for noncritical nets in physical design. In a GR process, a Steiner Minimum Tree (SMT) algorithm can be invoked millions of times, which means that SMT algorithm has great significance for the final quality of GR. Some of the research works are surveyed in this paper to understand GR and SMT problems and to learn the available solutions. Firstly, we systematically dissect three types of subproblems in Steiner tree construction and three types of GR methods. Then, we investigate the recent progress under two new technology models. Finally, the survey concludes with a summary of possible future research directions.

show abstract