Global optimization approach for architectural synthesis

Gebotys, Catherine H.; Elmasry, M.I.

doi:10.1109/43.240074

Cited by 93 publications

(15 citation statements)

References 14 publications

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“…In the early stage, Integer Linear Programming (ILP) based approaches [10], [15], [16] were widely investigated in HLS scheduling. For example, Gebotys and Elmasry [10] proposed a set of efficient formulas that can drastically reduce the solving time of ILP methods. By using a relaxed ILP formulation together with a greedy algorithm, Rim and Jain [15] presented an approach that can optimize lower bounds of operations.…”

Section: Related Workmentioning

confidence: 99%

Efficient Resource Constrained Scheduling Using Parallel Structure-Aware Pruning Techniques

Chen

Zhang

et al. 2016

IEEE Trans. Comput.

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Branch-and-bound approaches are promising in pruning fruitless search space during the resource constrained scheduling. However, such approaches only compare the estimated upper and lower bounds of an incomplete schedule to the length of the best feasible schedule at that iteration, which does not fully exploit the potential of the pruning during the search. Aiming to improve the performance of resource constrained scheduling, this paper proposes a parallel structure-aware pruning approach that can traverse the search space significantly faster than state-of-the-art branch-and-bound techniques. This paper makes three major contributions: i) it proposes an efficient pruning technique using the structural scheduling information of the obtained best feasible schedules; ii) it investigates how to perform parallel search to enable efficient multi-directional search and generation of effective fences by tuning the operation enumeration order; and iii) it presents a framework that supports the sharing of minimum upper-bound and fence information among different search tasks to enable efficient parallel structure-aware pruning. The experimental results demonstrate that our parallel pruning approach can drastically reduce the overall resource constrained scheduling time under a wide variety of resource constraints.

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Section: Related Workmentioning

confidence: 99%

Efficient Resource Constrained Scheduling Using Parallel Structure-Aware Pruning Techniques

Chen

Zhang

et al. 2016

IEEE Trans. Comput.

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“…Many different ILP models have been proposed [Camposano and Wolf 1991;Hwang et al 1991]. Chaudhuri and Walker [1994] and Gebotys and Elmasry [1993] have shown that efficient formulations lead to reduced execution times for the ILP approach. However, as the number of variables in the formulations increases very rapidly with the size of the DFG, even with efficient formulations, tight resource constraints can cause ILP models to take inordinately long to solve.…”

Section: Previous Workmentioning

confidence: 99%

A fast approach to computing exact solutions to the resource-constrained scheduling problem

Narasimhan

Ramanujam

2001

ACM Trans. Des. Autom. Electron. Syst.

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This article presents an algorithm that substantially reduces the computational effort required to obtain the exact solution to the Resource Constrained Scheduling (RCS) problem. The reduction is obtained by (a) using a branch-and-bound search technique, which computes both upper and lower bounds, and (b) using efficient techniques to accurately estimate the possible time-steps at which each operation can be scheduled and using this to prune the search space. Results on several benchmarks with varying resource constraints indicate the clear superiority of the algorithm presented here over traditional approaches using integer linear programming, with speed-ups of several orders of magnitude.

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“…Equation (23) ensures that each tail is allocated to one of the processors. Equation (25) ensures that no two tails are allocated to an identical processor.…”

Section: Ilp Model For Processor Allocationmentioning

confidence: 99%

ILP-based cost-optimal DSP synthesis with module selection and data format conversion

Ito

Lucke

Parhi

1998

IEEE Trans. VLSI Syst.

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In high-level synthesis, a data flow graph (DFG) description of an algorithm is mapped onto a register transfer level description of an architecture. Each node of the DFG is scheduled to a specific time and allocated to a processor. In this paper, we present new integer linear programming (ILP) models which generate a blocked schedule for a DFG with automatic retiming, pipelining, and unfolding while performing module selection and data format conversion. A blocked schedule is a schedule which overlaps multiple iterations of the DFG to guarantee a processor optimal schedule. During module selection an appropriate processor is chosen from a library of processors to construct a cost optimal architecture. Furthermore, we also include the cost and latency of data format conversions between processors of different implementation styles. We also present a new formulation for minimizing the unfolding factor of the blocked schedule. The approach presented in this paper is the only systematic approach proposed so far to include implicit unfolding and to perform synthesis using nonuniform processor styles and data format converters.

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Global optimization approach for architectural synthesis

Cited by 93 publications

References 14 publications

Efficient Resource Constrained Scheduling Using Parallel Structure-Aware Pruning Techniques

Efficient Resource Constrained Scheduling Using Parallel Structure-Aware Pruning Techniques

A fast approach to computing exact solutions to the resource-constrained scheduling problem

ILP-based cost-optimal DSP synthesis with module selection and data format conversion

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