Global Tiling for Communication Minimal Parallelization on Distributed Memory Systems

Liu, Lei; Chen, Li; Wu, Chunlin; Feng, Xiaobing

doi:10.1007/978-3-540-85451-7_41

Cited by 4 publications

(2 citation statements)

References 16 publications

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“…However, on distributed memory parallel systems, in order to attain load balancing and minimize data migration, the decomposition of computation and the distribution of data must be handled at the same time. In [12], Liu et al presented a global tiling method to select the optimal iteration space tiling and data space tiling, and thus improving parallelism and minimizing the volume of communication.…”

Section: Parallel Optimizationmentioning

confidence: 99%

New Methodologies for Parallel Architecture

Fan

2011

J. Comput. Sci. Technol.

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Moore's law continues to grant computer architects ever more transistors in the foreseeable future, and parallelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievements in our research project, which is supported by the National Basic Research 973 Program of China, on parallel architecture, are systematically presented. The innovative approaches and techniques to solve the significant problems in parallel architecture design are summarized, including architecture level optimization, compiler and language-supported technologies, reliability, power-performance efficient design, test and verification challenges, and platform building. Two prototype chips, a multiheavy-core Godson-3 and a many-light-core Godson-T, are described to demonstrate the highly scalable and reconfigurable parallel architecture designs. We also present some of our achievements appearing in ISCA, MICRO

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Section: Parallel Optimizationmentioning

confidence: 99%

New Methodologies for Parallel Architecture

Fan

2011

J. Comput. Sci. Technol.

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“…Bao et al [84] proposed a static compiler-based defensive tiling to choose the best tiling size for optimal performance. Some of the works related to loop tiling include [85,86] for the reduction of capacity misses, [87][88][89] for reducing communication, and [90][91][92] for auto/dynamic tuning of loop tiling.…”

Section: Data Access Optimizationmentioning

confidence: 99%

Data Locality in High Performance Computing, Big Data, and Converged Systems: An Analysis of the Cutting Edge and a Future System Architecture

Usman¹,

Mehmood

Katib

et al. 2022

Electronics

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Big data has revolutionized science and technology leading to the transformation of our societies. High-performance computing (HPC) provides the necessary computational power for big data analysis using artificial intelligence and methods. Traditionally, HPC and big data had focused on different problem domains and had grown into two different ecosystems. Efforts have been underway for the last few years on bringing the best of both paradigms into HPC and big converged architectures. Designing HPC and big data converged systems is a hard task requiring careful placement of data, analytics, and other computational tasks such that the desired performance is achieved with the least amount of resources. Energy efficiency has become the biggest hurdle in the realization of HPC, big data, and converged systems capable of delivering exascale and beyond performance. Data locality is a key parameter of HPDA system design as moving even a byte costs heavily both in time and energy with an increase in the size of the system. Performance in terms of time and energy are the most important factors for users, particularly energy, due to it being the major hurdle in high-performance system design and the increasing focus on green energy systems due to environmental sustainability. Data locality is a broad term that encapsulates different aspects including bringing computations to data, minimizing data movement by efficient exploitation of cache hierarchies, reducing intra- and inter-node communications, locality-aware process and thread mapping, and in situ and transit data analysis. This paper provides an extensive review of cutting-edge research on data locality in HPC, big data, and converged systems. We review the literature on data locality in HPC, big data, and converged environments and discuss challenges, opportunities, and future directions. Subsequently, using the knowledge gained from this extensive review, we propose a system architecture for future HPC and big data converged systems. To the best of our knowledge, there is no such review on data locality in converged HPC and big data systems.

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Defensive loop tiling for shared cache

Bao

Ding

2013

Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

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Global Tiling for Communication Minimal Parallelization on Distributed Memory Systems

Cited by 4 publications

References 16 publications

New Methodologies for Parallel Architecture

New Methodologies for Parallel Architecture

Data Locality in High Performance Computing, Big Data, and Converged Systems: An Analysis of the Cutting Edge and a Future System Architecture

Defensive loop tiling for shared cache

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