Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating

Amini, Esmail; Najibi, Mehrdad; Pedram, Hossein

doi:10.1109/isvlsi.2006.48

Cited by 24 publications

(10 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…On the other hand, the term GALS was first used by Chapiro in [10], having been successfully used in many implementations, including FPGAs [15] and ASIC (Application Specific Integrated Circuit) [13,14]. A GALS system consists of many synchronous functional modules (that may be IPs), which carries its own individual clock signals and communicate to each On the other hand, the ports proposed in [21][22][23] were specified in XBM (Extended Burst-Mode) and BM (Burst-Mode).…”

Section: Theorectical Backgroundmentioning

confidence: 99%

Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

Oliveira¹,

Faria²,

Lussari³

2020

JICS

View full text Add to dashboard Cite

Contemporary digital systems must be based on the “System-on-Chip – SoC” concept. An interesting style for SoC design is the GALS paradigm (Globally Asynchronous, Locally Synchronous), which can be used to implement circuits in FPGAs (Field Programmable Gate Arrays). However the implementation of asynchronous interfaces (asynchronous wrapper – AW) constitutes a major drawback for this kind of devices. Although there is a typical AW design style, which is based on asynchronous controllers providing communication between modules (called ports), port controllers are subject to essentialhazard when implemented in FPGAs. In this context, this paper proposes a new asynchronous GALS wrapper architecture, suitable for implementations in any kind of FPGAs. The proposed port controllers showed to be essential-hazard-free, not needing any special cares in implementation concerning to LUTs choice. Additional advantages of the proposed architecture are: total autonomy that synchronous modules achieve when interacting with the asynchronous wrapper; the ports can be synthesized in the direct mapping style (so without knowledge of asynchronous logic synthesis); and the ports interact with environment in Ib/Ob Mode, not needing a timing analysis. Simulation results show the applicability of the proposed architecture and lead to its practical implementations in FPGAs.

show abstract

Section: Theorectical Backgroundmentioning

confidence: 99%

Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

Oliveira¹,

Faria²,

Lussari³

2020

JICS

View full text Add to dashboard Cite

show abstract

“…However, before such system optimization can be achieved, a few obstacles need to be overcome such as the special interface modules used for handling synchronous and asynchronous designs called wrappers [4,5]. The wrappers surround each locally synchronous module and are responsible for all synchronous/asynchronous transactions.…”

Section: Introductionmentioning

confidence: 99%

“…Conclusions and future works can be found in the last section. through the transmission process [4].…”

Section: Introductionmentioning

confidence: 99%

GALS system optimization using retiming concept

Sedighi

Farrokhi

2010

IEICE Electron. Express

View full text Add to dashboard Cite

Significant efforts have been put into optimization of GALS systems by considering locally synchronous modules as individual and independent islands of circuits. While existing approaches do improve some of the system characteristics, due to their limited scope, their achieved improvement is often limited too. This paper proposes an optimization approach in which a GALS system is optimized as a whole. The approach allows combinational or sequential sub-modules to move from one synchronous module to another while preserving the GALS system functionality. Experimental results show that if the movements are done properly, the proposed approach provides better results than the existing methods. The application of the proposed approach on benchmark circuits demonstrates 15.8% latency reduction with 3.3% area overhead in average.

show abstract

“…In these cases, an off-chip oscillator has to be used to generate a stable stoppable on-chip clock. There have been two proposal of how to use an external oscillator in a GALS environment [9], [10]. Both use a transistor based design to be able to start and stop the local clock.…”

Section: Introductionmentioning

confidence: 99%

“…Both use a transistor based design to be able to start and stop the local clock. E. Amani et al [10] might have a problem DATAi+1 REQi+l -ACKj+, with metastability in their circuit. If the local clock is gated and the start signal for the local clock has an event at the same time as the external clock, a metastable state could occur in the circuit and could lead to a glitch on the local clock.…”

Section: Introductionmentioning

confidence: 99%

A Clock Gating Circuit for Globally Asynchronous Locally Synchronous Systems

2006

View full text Add to dashboard Cite

This paper proposes a circuit that enables the use of off-chip oscillators in a Globally Asynchronous Locally Synchronous system. Usually, a local oscillator is used, which can be stopped. However, a local oscillator, e.g., ring oscillator, is not as stable as an off-chip oscillator and is therefore problematic to use for certain applications. The proposed circuit also informs the local synchronous module if the local clock has been stopped for too many of the off-chip oscillators clock cycles, so that it can take appropriate actions, e.g., recalibrate ring oscillators. The circuit has been tested in an Altera Stratix II FPGA and simulated in a 0.35 ,um CMOS process.

show abstract

Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating

Abstract: Abstract

Cited by 24 publications

References 6 publications

Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

GALS system optimization using retiming concept

A Clock Gating Circuit for Globally Asynchronous Locally Synchronous Systems

Contact Info

Product

Resources

About