Globally integrated power and clock distribution network

Abstract

Abstract-The global networks within a conventional integrated circuits (IC) consists of three major types: power, ground, and clock networks. These three networks consumes most of the metal resources in the highest metal layers. The signals traversing the power and clock distribution networks are fundamentally different in terms of signal frequency and current flow. Combining the power and clock network into a globally integrated network is therefore possible. In this paper, the general concept of a globally integrated power and clock (GIPAC) system is proposed. The circuitry supporting this GIPAC system is also presented. Simulation results based on a 90 nm CMOS technology demonstrate the potential of GIPAC.

Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks

“…Experimental results on industrial designs show that the power consumption is reduced by up to 47.9% compared to square-wave conventional CDNs. https://www.indjst.org/ A globally integrated power and clock (GIPAC) distribution network was proposed in (37) as a means of eliminating the on-chip global clock distribution network. The power and clock signals are integrated in the GIPAC and then separated in the local power and local clock networks using a low-pass and high-pass filters, respectively.…”

Effect of integrated power and clock networks on combinational circuits

“…A primary consumer of power on-chip is the Clock Distribution Network or the Clock Tree. Traditionally, it wa consumes anywhere between 30% to 50 % of the total dynamic power [1][2][3][4][5].…”

“…The research articles which have been published on GIPAC [1] include various methods for decreasing energy usage in circuits. Earlier literature had tried merging power and clock signals throughout the chip.…”

“…Earlier literature had tried merging power and clock signals throughout the chip. The combined signals were filtered and two signals were obtained from the GIPAC [1] [2], totally by merging the two networks. Newer literature on combinatorial wire-wireless clock distribution networks [3] suggests a combined circuit consisting of wired and wireless clock networks.…”

“…Earlier literature had tried merging power and clock signals throughout the chip. The combined signals were filtered and two signals were obtained from the GIPAC [1] network. Higher frequency signal is the clock signal and the signal with a constant dc value is Vcc or the power signal.…”