Godson-3: A Scalable Multicore RISC Processor with x86 Emulation

Hu, Weiwu; Wang, Jian; Gao, Xiang; Chen, Tianshi; Liu, Qi; Li, Guojie

doi:10.1109/mm.2009.30

Cited by 86 publications

(50 citation statements)

References 10 publications

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“…Except for the content-based approach, there are topic/channel-based pub/sub systems that support only a limited number of communication channels [3]. Low energy processor units [28], [29] are an important enabling technology to HUNETs. A survey of the application of the Bloom filter in computer networks is in [30].…”

Section: Related Workmentioning

confidence: 99%

The Design and Evaluation of An Information Sharing System for Human Networks

Zhao¹,

Wu²

2014

IEEE Trans. Parallel Distrib. Syst.

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Abstract-With fast-growing consumer demands and rapidly-developing mobile technologies, portable mobile devices are becoming a necessity of our daily lives. However, existing mobile devices rely on the wireless infrastructure to access Internet services provided by central application providers. This architecture is inefficient in many situations and also does not utilize abundant interdevice communication opportunities in many scenarios. This paper proposes the human network (HUNET), a network architecture that enables information sharing between mobile devices through direct interdevice communication. We design B-SUB, an interest-driven information sharing system for HUNETs. In B-SUB, content and user interests are described by tags, which are human-readable strings that are designated by users. An experiment is performed to demonstrate the effectiveness of this tag-based content description method. To facilitate efficient data dissemination, we invent the Temporal Counting Bloom filter (TCBF) to encode tags, which also reduces the overhead of content routing. Comprehensive theoretical analyses on the parameter tuning of B-SUB are presented and verify B-SUB's ability to work efficiently under various network conditions. We then extend B-SUB's routing scheme to provide a stronger privacy guarantee. Extensive real-world trace-driven simulations are performed to evaluate the performance of B-SUB, and the results demonstrate its efficiency and usefulness.Index Terms-Content-based publish/subscribe, interest-driven information sharing, human network, bloom filter

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Section: Related Workmentioning

confidence: 99%

The Design and Evaluation of An Information Sharing System for Human Networks

Zhao¹,

Wu²

2014

IEEE Trans. Parallel Distrib. Syst.

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“…Godson-3B is the second chip of the Godson-3 Chip Multi-Processor (CMP) series [25][26] , which is targeted at high-performance scientific computing, high-end embedded applications, and high-throughput server applications. To achieve scalability, the interconnection network of Godson-3 employs a mesh+crossbar topology.…”

Section: Architecture Parameters Of Godson-3bmentioning

confidence: 99%

“…From (26), data shuffle takes more than 28% time of T c . Thus, dedicated MADD-shuffle-mixed vector instructions can greatly reduce the time of shuffling twiddle factors as well as temporary data, and reduce the vector instructions s (which is 5 currently) needed to compute v butterflies.…”

Section: Fft Performance Analysis On Gs464v Corementioning

confidence: 99%

An FFT Performance Model for Optimizing General-Purpose Processor Architecture

Chen

Liu

et al. 2011

J. Comput. Sci. Technol.

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General-purpose processor (GPP) is an important platform for fast Fourier transform (FFT), due to its flexibility, reliability and practicality. FFT is a representative application intensive in both computation and memory access, optimizing the FFT performance of a GPP also benefits the performances of many other applications. To facilitate the analysis of FFT, this paper proposes a theoretical model of the FFT processing. The model gives out a tight lower bound of the runtime of FFT on a GPP, and guides the architecture optimization for GPP as well. Based on the model, two theorems on optimization of architecture parameters are deduced, which refer to the lower bounds of register number and memory bandwidth. Experimental results on different processor architectures (including Intel Core i7 and Godson-3B) validate the performance model.The above investigations were adopted in the development of Godson-3B, which is an industrial GPP. The optimization techniques deduced from our performance model improve the FFT performance by about 40%, while incurring only 0.8% additional area cost. Consequently, Godson-3B solves the 1024-point single-precision complex FFT in 0.368 µs with about 40 Watt power consumption, and has the highest performance-per-watt in complex FFT among processors as far as we know. This work could benefit optimization of other GPPs as well.

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“…Godson-3 processors [10] are used in the experiments. Godson-3 is the third generation of the Godson microprocessor series, a project of the Institute of Computing Technology of the Chinese Academy of Sciences.…”

Section: A Experiments Platformmentioning

confidence: 99%

Efficient binary translation system with low hardware cost

Liu

Wang

et al. 2009

2009 IEEE International Conference on Computer Design

Self Cite

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Abstract-Binary translation is one of the most important approaches for system migration. However, software binary translation systems often suffer from the inefficiency and traditional hardware-software co-designed virtual machines require the unavoidable re-design of the processor architecture. This paper presents a novel hardware-software co-designed method to accelerate the binary translation on an existing architecture. The hardware supports for source-architecture-only functions, partial decodes and binary translation system acceleration are proposed. These hardware supports help the binary translation system to achieve high performance and simplify the design of the binary translation software. In the meantime, the hardware cost is well controlled in a certain low level. These supports are implemented in Godson-3 processors to speedup the x86 binary translation to the native MIPS instruction set. Performance evaluations on RTL simulation and FPGA emulation platforms show that the proposed method can speedup most benchmark programs by nearly 10 times compared to pure software-based binary translation and achieves about 70% performance of the native program execution. The chip is fabricated in ST 65nm CMOS technology, and the physical design results show that the chip area cost is less than 5%.

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Godson-3: A Scalable Multicore RISC Processor with x86 Emulation

Cited by 86 publications

References 10 publications

The Design and Evaluation of An Information Sharing System for Human Networks

The Design and Evaluation of An Information Sharing System for Human Networks

An FFT Performance Model for Optimizing General-Purpose Processor Architecture

Efficient binary translation system with low hardware cost

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