GOI fabrication for monolithic 3D integration

Abedin, Ahmad; Žurauskaitė, Laura; Asadollahi, Ali; Garidis, Konstantinos; Jayakumar, Ganesh; Malm, B. Gunnar; Hellström, Per‐Erik; Östling, Mikael

doi:10.1109/s3s.2017.8309201

Cited by 3 publications

(5 citation statements)

References 7 publications

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“…Firstly, TDDs in the Ge absorption layer are still high. To eliminate the TDDs, numerous strategies were proposed in recent decades, including doped Ge buffer layers [ 108 , 109 , 110 ], compositionally graded SiGe buffer layers [ 111 , 112 , 113 ], ultra-thin Si/SiGe superlattice buffer layers [ 114 , 115 ], high temperature annealing [ 116 , 117 , 118 ], three-step growth [ 119 , 120 ], the selective epitaxial growth (SEG) method [ 121 , 122 , 123 ], etc. With the continuous effort focused on decreasing the TDDs in the Ge layer, the TDDs for the top Ge layer were evaluated to be in the orders of 10 6 –10 7 cm −2 .…”

Section: Swir Apds Focal Plane Arrays (Fpas)mentioning

confidence: 99%

Review of Ge(GeSn) and InGaAs Avalanche Diodes Operating in the SWIR Spectral Region

Miao¹,

Lin²,

Li³

et al. 2023

Nanomaterials

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Among photodetectors, avalanche photodiodes (APDs) have an important place due to their excellent sensitivity to light. APDs transform photons into electrons and then multiply the electrons, leading to an amplified photocurrent. APDs are promising for faint light detection owing to this outstanding advantage, which will boost LiDAR applications. Although Si APDs have already been commercialized, their spectral region is very limited in many applications. Therefore, it is urgently demanded that the spectral region APDs be extended to the short-wavelength infrared (SWIR) region, which means better atmospheric transmission, a lower solar radiation background, a higher laser eye safety threshold, etc. Up until now, both Ge (GeSn) and InGaAs were employed as the SWIR absorbers. The aim of this review article is to provide a full understanding of Ge(GeSn) and InGaAs for PDs, with a focus on APD operation in the SWIR spectral region, which can be integrated onto the Si platform and is potentially compatible with CMOS technology.

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Section: Swir Apds Focal Plane Arrays (Fpas)mentioning

confidence: 99%

Review of Ge(GeSn) and InGaAs Avalanche Diodes Operating in the SWIR Spectral Region

Miao¹,

Lin²,

Li³

et al. 2023

Nanomaterials

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“…After substantial optimization of the interfacial layer/ high-k stack, state-of-the-art interface state densities (Dit) in the low 10 11 eV -1 cm -2 range. This process was also used to fabricate fully depleted Ge devices (24,25). Although the interface state density is adequate for transistors, there is still an issue with charging/discharging of oxide traps leading to threshold voltage instabilities that are not compatible with high performance CMOS devices.…”

Section: High Performance Gate Dielectrics On Gementioning

confidence: 99%

“…However, the fabricated devices show a 60% higher hole mobility compared to Si pFET reference, demonstrating the potential for high performance Ge pFET devices. The transfer characteristics also show effects of non-overlapping drain current at low and high VDS, probably due to oxide traps in the GeO2 interfacial layer gate stack employed in the fabricated transistors(27). The project has made a substantial contribution to the state-of-…”

mentioning

confidence: 98%

(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS

Ostling,

Hellstrom

2023

ECS Trans.

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To keep the scaling progress going, we must go three dimensional (3D). This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects. By stacking the transistors on top of each other, and connecting them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature than today’s Si CMOS technology. Here, we have focused on Ge based transistors, which have an inherently lower process temperature compared to Si transistors. Several technological and design breakthroughs towards realizing Ge based sequential 3D circuits are discussed.

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“…For extremely thin Ge at 150 nm, the optical efficiency is reduced from 80% to 60%, remaining high enough. A thin absorbing layer could be interesting from the fabrication point of view because it will not cause wafer bending or elongated threading dislocations due to lattice mismatch with the Si substrate 25 . The simulation helps to determine the tradeoff between the thinner Ge and optical efficiency.…”

Section: Design and Optical Simulationmentioning

confidence: 99%

“…A thin absorbing layer could be interesting from the fabrication point of view because it will not cause wafer bending or elongated threading dislocations due to lattice mismatch with the Si substrate. 25 The simulation helps to determine the tradeoff between the thinner Ge and optical efficiency. Besides it, thinner Ge allows a faster device.…”

Section: Design and Optical Simulationmentioning

confidence: 99%

Single microhole per pixel for thin Ge-on-Si complementary metal-oxide semiconductor image sensor with enhanced sensitivity up to 1700 nm

et al. 2023

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.We present a germanium “Ge-on-Si” CMOS image sensor with backside illumination for the near-infrared (NIR) electromagnetic waves (wavelength range 300 to 1700 nm) detection essential for optical sensor technology. The microholes help to enhance the optical efficiency and extend the range to the 1.7-μm wavelength. We demonstrate an optimization for the width and depth of the microholes for maximal absorption in the NIR. We show a reduction in the crosstalk by employing thin SiO2 deep trench isolation in between the pixels. Finally, we show a 26 to 50% reduction in the device capacitance with the introduction of a microhole. Such CMOS-compatible Ge-on-Si sensors will enable high-density, ultrafast, and efficient NIR imaging.

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GOI fabrication for monolithic 3D integration

Cited by 3 publications

References 7 publications

Review of Ge(GeSn) and InGaAs Avalanche Diodes Operating in the SWIR Spectral Region

Review of Ge(GeSn) and InGaAs Avalanche Diodes Operating in the SWIR Spectral Region

(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS

Single microhole per pixel for thin Ge-on-Si complementary metal-oxide semiconductor image sensor with enhanced sensitivity up to 1700 nm

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