Golden Reference-Free Hardware Trojan Localization Using Graph Convolutional Network

Abstract

The globalization of the Integrated Circuit (IC) supply chain has moved most of the design, fabrication, and testing process from a single trusted entity to various untrusted thirdparty entities worldwide. The risk of using untrusted third-Party Intellectual Property (3PIP) is the possibility for adversaries to insert malicious modifications known as Hardware Trojans (HTs). These HTs can compromise the integrity, deteriorate the performance, deny the service, and alter the functionality of the design. While numerous HT detection methods have been proposed in the literature, the crucial task of HT localization is overlooked. Moreover, a few existing HT localization methods have several weaknesses: reliance on a golden reference, inability to generalize for all types of HT, lack of scalability, low localization resolution, and manual feature engineering/property definition. To overcome their shortcomings, we propose a novel, golden reference-free HT localization method at the pre-silicon stage by leveraging Graph Convolutional Network (GCN). In this work, we convert the circuit design to its intrinsic data structure, graph and extract the node attributes. Afterward, the graph convolution performs automatic feature extraction for nodes to classify the nodes as Trojan or benign. Our approach is automated and does not burden the designer with manual code review. It locates the Trojan signals with 99.6% accuracy, 93.1% F1-score, and a false-positive rate below 0.009%.

A Siamese Deep Learning Framework for Efficient Hardware Trojan Detection Using Power Side-Channel Data

“…The focal point of this section revolves around HTD utilizing the "Hardware Trojan Power & EM Side-Channel" dataset obtained from IEEE DataPort 41 . The IEEE dataset is a comprehensive collection of single-dimensional time series readings for power and EM side-channel signals, Fig.…”

DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer

“…According to the lifecycle of integrated circuits, HT detection techniques can be categorized into pre-silicon and post-silicon detection techniques. Yasaei et al [8] convert the HDL code of the circuit into a specific data flow graph in the pre-silicon stage, and then they use a graph convolutional network (GCN) to classify the nodes in the graph to determine whether they are infected by HTs, achieving HT detection and localization. Lyu and Mishra [9] map the activation problem of HT trigger logic to the maximum clique cover problem and propose a test vector generation algorithm based on maximal clique sampling to increase the probability of activating hidden HTs, thereby improving the HT detection rate.…”